feature article
Subscribe Now

Lattice Lives on the Edge

Company Focused after Failed Acquisition

A year ago, Lattice Semiconductor was all set to be acquired by Canyon Bridge Partners, a “global private equity buyout fund headquartered in Palo Alto, California” for $1.3B. The industry lamented the loss of another independent FPGA company, with Xilinx and Achronix remaining the only two independent FPGA vendors, after Actel, SiliconBlue, and Altera had all been gobbled up by larger suitors.

The Lattice deal had some unusual properties, however. Unlike the other FPGA acquisitions, Canyon Bridge Partners was not a technology company expanding its portfolio. It turns out that some special parsing was required on Canyon Bridge. What was touted as “A global private equity buyout fund headquartered in Palo Alto, California” whose management team had “deep roots in Silicon Valley” – actually translated into “Chinese government-backed private equity fund.” The US government, leery of losing key technology to Chinese government ownership, blocked the acquisition this fall, only the fourth time such an acquisition has been blocked due to national security concerns.

While this may have made Lattice feel like their country loved and valued them, it would appear to leave Lattice in a bit of a quandary. How would the company move forward following the failed acquisition and the many months of radio silence that surrounded the ill-fated deal?

We visited Lattice headquarters this month and talked to their management team, including Glen Hawk, the company’s COO. Luckily, Lattice has a solid strategy for moving forward, and it fortuitously fits the current market trends like a glove.

Over the last decades, Lattice has struggled to get out of the formidable shadows of FPGA leaders Xilinx and Altera. Lattice’s early strength was complex programmable logic devices (CPLDs), which were the smaller, lighter precursors to field programmable gate arrays (FPGAs). As FPGAs gained dominance, CPLDs were relegated to low-end, low-margin “glue logic” applications. Finally, even the CPLD architecture itself became unsustainable and the CPLD market was taken over by smaller, cheaper FPGAs.

Lattice never competed directly with the high-end offerings of Xilinx and Altera, but they defended the low end ferociously. However, as designs and devices grew more complex, many sockets that would have gone to CPLD-class devices were swallowed up in integration plays into larger FPGAs or other components. This left Lattice struggling to differentiate itself against formidable competitors with much wider ranges of solutions.

Lattice made several smart moves in order to pull out of this corner. First, they launched a very competitive line of low-cost FPGAs dubbed “ECP” ( rumored to be known inside the company as “el cheapo”). These devices fared well against mostly-neglected parts of the big vendors’ low-end lines, with features that targeted specific types of high-value applications.

More significant, however, was Lattice’s acquisition of SiliconBlue in 2012. SiliconBlue brought highly-differentiated FPGAs designed specifically for ultra-low power, ultra-low cost, high-volume applications such as mobile devices. These devices gave Lattice access to a whole new market, and a whole new identity. Touting the iCE family as the “World’s Smallest FPGAs,” Lattice captured the dominant share of the programmable logic market for mobile and high-volume consumer applications. With chips measuring a couple millimeters on a side, with sub-$1 price tags and sipping microwatts, no other FPGA was remotely close to the requirements of the mobile device crowd. The only slightly comparable competitive offerings were those of QuickLogic, who – while continuing to sell FPGA-based devices – has dropped the “FPGA” label in favor of “CSSP” or “customer-specific standard products” (code name for “FPGA that we design for you”).

Lattice found good success in various consumer applications, and then, in 2015, acquired Silicon Image, bringing an interesting addition to its consumer-centric portfolio with, among other things, wired and wireless connectivity technology that dovetails nicely with Lattice’s existing offerings. This combination of strengths – CPLD, mid-range FPGA, ultra-low power FPGA, and related connectivity and consumer-related IP put the company in a great position to exploit the IoT explosion – positioning itself as indispensable in edge applications for control, connectivity, and compute acceleration.

At about the same time, however, Tsinghua Holdings announced that it had acquired a significant interest in the company’s shares, sending Lattice (perhaps unwittingly) into the waiting arms of the ill-fated Canyon Bridge acquisition. The company went dark, and the well-conceived assault on the edge of the IoT fell into the shadows.

Now, however, the cloak of darkness has lifted, and Lattice is living on the edge. The company is at full steam following the course they set a couple years ago, capturing applications at the edge of the IoT where power, cost, and form-factor are at a premium, connectivity, control, and compute requirements are changing rapidly, and programmability is a huge asset. In numerous applications – from wearables and smartphones to VR headsets to drones to automotive ADAS to industrial automation – Lattice is experiencing success with its entire portfolio, often all in the same design.

Recently, the company has demonstrated programmable neural network accelerators delivering 1 Tera Ops while consuming less than 1 watt. While not up to the power of high-end neural network accelerators, the tiny power budget makes edge-based computing practical for numerous applications that can’t afford the latency and risk of offloading compute tasks to the cloud. For example, Lattice has demonstrated face detection (“Yep, that’s a face”) with a binary neural network (BNN) implementation on its iCE40 UltraPlus devices operating at less than 5mW. Upgrade to full-fledged face tracking (“That’s the face right there – now it’s there – now it’s there”) and Lattice can handle it with their ECP5 FPGA implementing a convolutional neural network (CNN) at less than one watt.

This is primarily where the line has been drawn between Lattice and other FPGA companies. While traditional FPGA companies like Xilinx and Intel (Altera) are going for the largest, fastest, most highly-integrated devices they can muster, taking advantage of advanced FinFET technologies to cram the most possible stuff onto their chips, Lattice uses FD-SOI processes to milk out the most performance possible with the tiniest power budgets and lowest device cost. The difference in the two strategies is so dramatic, there will probably seldom be a socket where Lattice competes directly with another FPGA company offering (other than traditional CPLD applications). Xilinx and Intel (Altera) FPGAs will land in data centers and higher-end applications where power, price, and footprint are less precious, and Lattice will own the edge where pennies and millimeters and microwatts are at a premium.

It’s too early to know for sure how much market Lattice will be able to capture with this strategy, but, at the moment, they seem to be running mostly unopposed. In most cases, alternative solutions require considerably different approaches, so Lattice is able to make a strong case for their value. That may or may not translate into the kind of margins the company needs to sustain and feed growth and to keep up with the engineering investment required to move their technology forward and keep it competitive with emerging competitive solutions. For now, though, Lattice looks to be positioned well to succeed in their goals. It will be interesting to watch.

 

Leave a Reply

featured blogs
Oct 23, 2020
Processing a component onto a PCB used to be fairly straightforward. Through hole products, a single or double row surface mount with a larger center-line rarely offer unique challenges obtaining a proper solder joint. However, as electronics continue to get smaller and conne...
Oct 23, 2020
[From the last episode: We noted that some inventions, like in-memory compute, aren'€™t intuitive, being driven instead by the math.] We have one more addition to add to our in-memory compute system. Remember that, when we use a regular memory, what goes in is an address '...
Oct 23, 2020
Any suggestions for a 4x4 keypad in which the keys aren'€™t wobbly and you don'€™t have to strike a key dead center for it to make contact?...
Oct 23, 2020
At 11:10am Korean time this morning, Cadence's Elias Fallon delivered one of the keynotes at ISOCC (International System On Chip Conference). It was titled EDA and Machine Learning: The Next Leap... [[ Click on the title to access the full blog on the Cadence Community ...

featured video

Better PPA with Innovus Mixed Placer Technology – Gigaplace XL

Sponsored by Cadence Design Systems

With the increase of on-chip storage elements, it has become extremely time consuming to come up with an optimized floorplan with manual methods. Innovus Implementation’s advanced multi-objective placement technology, GigaPlace XL, provides automation to optimize at scale, concurrent placement of macros, and standard cells for multiple objectives like timing, wirelength, congestion, and power. This technology provides an innovative way to address design productivity along with design quality improvements reducing weeks of manual floorplan time down to a few hours.

Click here for more information about Innovus Implementation System

featured paper

Fundamentals of Precision ADC Noise Analysis

Sponsored by Texas Instruments

Build your knowledge of noise performance with high-resolution delta-sigma ADCs. This e-book covers types of ADC noise, how other components contribute noise to the system, and how these noise sources interact with each other.

Click here to download the whitepaper

Featured Chalk Talk

MCU32 Graphics Overview

Sponsored by Mouser Electronics and Microchip

Graphical interfaces add a whole new dimension to embedded designs. But, designing a full-blown graphics interface is a major challenge for most embedded systems designers. In this episode of Chalk Talk, Amelia Dalton and Kurt Parker from Microchip Technology explain how you can add a modern graphics user interface to your next embedded design without a big learning curve.

Click here for more information about Microchip Technology MPLAB® X Integrated Development Environment