The winds of change are blowing strongly in the FPGA market these days. As programmable logic has matured, a number of lucrative market opportunities have opened up, driven by the rapid deployment of 5G, the revolution in application of AI technology across numerous design types, the transformation of the data center into a complex heterogeneous computing cluster, the overhaul of automotive and transportation technology, and the explosion of new IoT applications. All of these trends are contributing to an unprecedented growth in the amount of data being generated, transported, stored, processed, and used.
FPGAs are strong in all of the areas required to meet those demands. They have always been critical in the networking and data movement space, and they have more recently become adept at handling acceleration tasks for applications where Von Neumann machines are inefficient (such as AI inference). But the factor that has driven FPGA adoption more than anything is change. Any time a new application is evolving and changing rapidly, FPGAs bring engineering teams the ability to quickly adapt to that change and get working products into the field. But the adoption of FPGAs has always been hampered by the challenge teams face in designing with them, and their comparatively high cost and lack of efficiency.
Intel made a pair of announcements this week that should make it easier for new teams to adopt FPGAs, and for existing FPGA-based applications to evolve, reduce cost, and improve performance and power consumption as their systems go from prototype to early deployment to mass production, and as the standards continue to evolve throughout that life cycle. First is the announcement of the Intel Open FPGA stack – a new, open framework for designing systems with FPGA-based acceleration. Second is the announcement of a new version of the eASIC structured ASIC technology – the first new version since Intel acquired eASIC in 2018. You may see a couple of words in there that you aren’t used to, particularly in Intel press releases. “Structured ASIC” is a term that many of us thought went the way of the dodo years ago, and few people who follow Intel have ever seen the word “Open” anywhere near the blue Intel logo.
Looking first at the Open FPGA stack (OFS), Intel says it “offers hardware, software, and application developers a scalable, source-accessible infrastructure with standard interfaces and APIs that enables them to build custom acceleration platform solutions. Developers are already using this second-generation hardware and software infrastructure to develop solutions based on Intel and third-party platforms featuring the Intel Stratix 10 and Intel Agilex FPGA solutions. All Intel OFS hardware and software code has been developed using an open source development methodology. Users are granted access to the source code – which Intel refers to as “source accessible.“ Ok, so not “open source” per-se, but hey, we are headed in the right direction here.
Developing FPGA-based accelerators is a daunting challenge. The basics seem simple enough – find the most compute-intensive parts of your application and implement them in FPGA hardware, then modify the software to farm those parts out to the attached FPGA hardware rather than the main applications processor. But the devil is most certainly in the details. How does the applications processor communicate with the FPGA accelerator? How is data passed back and forth? Is there direct memory access? Buses? Are you supporting a specific hardware configuration of FPGA and processor, or are you trying to build an application that is easily portable to multiple heterogeneous compute platforms? OFS should help to simplify a lot of those issues, and, because it is “source accessible,” it allows you to pick and choose pre-designed components and modules to use in your design, as well as modifying or customizing those that don’t quite meet your needs out of the box.
The openness is interesting here because FPGA companies famously try to offer “sticky” IP and tools, meaning they build in a lot of value that encourages teams to adopt their solutions. But once you take the plunge and use those technologies, you are effectively locked into that vendor’s hardware and ecosystem. By making these tools “source accessible,” you could theoretically adapt them to any combination of vendors’ hardware, software, and IP architecture. That appears to be a step forward for the industry.
Moving on to the eASIC announcement, Intel has an interesting and unique strategy at play that affects everything from adoption of their FPGA technology to long-term ownership of application sockets. Historically, FPGAs are heavily used for prototyping and early production. In that situation, the flexibility they provide is incredibly valuable, allowing teams to adapt to changes in product specs, industry standards, and so forth – without taking the enormous cost and risk of developing custom ASICs. It allows teams to get working hardware to market fast, with minimal risk. But, as solutions mature, the cost, performance, and lack of power efficiency of FPGAs become a liability. Teams then often abandon the FPGA solutions in favor of custom ASIC or ASSPs that reduce unit cost, improve performance, and reduce power consumption.
With the eASIC solution, design teams can take stable chunks of design that were previously implemented in FPGA and replace them with a “hardened” eASIC equivalent with minimal cost and risk. The eASIC technology is designed from the ground up to convert FPGA designs into power-, performance-, and cost-optimized silicon with virtually no re-design work and a tiny fraction of the NRE, risk, and schedule associated with normal ASIC development. The ongoing expansion of system-in-package/chiplet technology such as Intel’s embedded multi-die interconnect bridge (EMIB) compounds the eASIC advantage. Now, teams can theoretically drop an eASIC chiplet into their SiP to replace some programmable logic while keeping the rest of the design intact. And, if the design relies on at least some programmable fabric component long-term, they can reduce the size of the programmable logic and gain the performance and power efficiency as well as some cost reduction – with minimal re-engineering.
While eASIC has been around for years, Intel says the new eASIC N5X “is the first structured eASIC family with an Intel FPGA compatible hard processor system. The Intel eASIC N5X helps customers migrate both their custom logic and designs — using the embedded hard processor in the FPGA — to structured ASICs, bringing benefits like lower unit cost, faster performance and reduced power consumption.” This is significant because a growing number of designs take advantage of the built-in ARM-based embedded processing system on some Intel FPGAs. By bringing that infrastructure into the eASIC version, a one-to-one mapping of a complete FPGA SoC design into ASIC becomes enormously easier.
Also worth noting is that eASIC has the ability to map designs from other FPGA technologies as well. This gives Intel the opportunity to steal sockets away that were previously owned by competitors when the time comes for cost reduction. Often, this happens when volume production is about to ramp, so with competitors (OK, we are primarily talking about Xilinx here) offering no comparable solution, Intel can potentially grab customers away just before the big payday.
Speaking of Xilinx, it will be interesting to watch what happens next in the FPGA market. It’s been about five years since Intel acquired Altera, and we’d guess that the company took about a two-year hit in their competitive position due to the inevitable fallout from the acquisition. Now, after the usual staff changes, reorganizations, leadership changes, and so forth – Intel seems to be settling into a groove with their FPGA strategy. At the same time, AMD is in the process of acquiring Xilinx, which will most likely throw the brakes on that company’s progress in a similar fashion. It is too early to tell how this will affect the programmable logic competition between Intel and AMD, at the same time the market for programmable logic is positioned for explosive growth with 5G, AI, cloud, and IoT build-out.
