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IBM Research Fellow Robert H. Dennard, 1932-2024: Inventor of the DRAM, Formulated MOS Scaling Law

Robert Dennard spent more than half a century working at one company: IBM. During his tenure at IBM, Dennard worked on a variety of advanced electronics projects; however, he’s best remembered for two major accomplishments: he invented the DRAM and was the first person to observe and formulate the advantageous scaling of speed and power consumption with size in MOS semiconductors, a phenomenon that lasted for more than three decades and became known as Dennard Scaling. Robert Dennard died on April 23, 2024, at the age of 91.

Robert Dennard. Image credit: IBM

Dennard was born in 1932, during the Great Depression. His father was a dairy farmer and his family lived in Terrell, Texas, about an hour’s drive from Dallas. In 1941, the Dennard family moved to Irving, a small Texas town near Dallas that is now part of the Dallas-Fort Worth megalopolis.

As a boy, Dennard’s main interests were shooting his BB gun and riding the farm’s horse. By the sixth grade, Dennard had discovered science fiction and became an avid reader. He also appreciated Ogden Nash poems and operettas written by the Hungarian-American composer Sigmund Romberg. Dennard attended high school in Irving and found it unchallenging. His high school guidance counselor noted Dennard’s aptitude in math and recommended engineering as a possible profession. Having nothing better in mind, that recommendation set Dennard’s path in life. Certainly, his interest in science fiction during its Golden Age also helped to guide that path.

Arlington State Junior College was nearby and Dennard considered enrolling because he’d be able to commute from home. The junior college taught engineering classes, and many of Dennard’s classmates planned to attend there. However, Dennard played the E-flat bass horn in the high school band, which snagged him a band scholarship at Southern Methodist University (SMU) in Dallas. The commute was a bit longer, but Dennard was still able to live at home. After his freshman year at SMU, Dennard joined a co-op program and alternated between eight weeks at school and eight weeks working for the Dallas Power and Light Company. At SMU, Dennard took general engineering classes (material science, civil engineering, elementary electrical engineering) and found calculus particularly interesting. He graduated from SMU with a bachelor’s degree in 1954 and a master’s degree in 1956.

After graduating from SMU, Dennard accepted a graduate fellowship at Carnegie Tech (now Carnegie Mellon University). He did his thesis work on subharmonic oscillations in magnetic resonant circuits under Professor Leo Finzi, who was an authority on magnetic amplifiers, a circuit element commonly used for power control and low-frequency amplification during the 1940s and 1950s. Upon receiving his PhD in 1958, Dennard interviewed with Bell Labs, General Electric, and IBM, which was just starting to build the Thomas J. Watson Research Center in Yorktown Heights, New York. Dennard accepted a position with IBM Research, as did many of his Carnegie Tech friends during a hiring boom at IBM. He worked there for his entire professional career, which spanned more than five decades.

Dennard spent his first two years at IBM Research working on resonant circuits. The work was similar and related to his PhD work on magnetic amplifiers but was aimed at developing ternary (base 3) logic. He also worked on magnetostrictive (acoustic) memory storage during that time. Dennard’s next project involved developing a 4800bps modem for data communications over telephone lines. This project gave Dennard the opportunity to travel to London and Rome to demonstrate the modem’s capabilities. It was his first trip to Europe.

Next, Dennard started working for George Feth, whom he’d known at Carnegie Tech. Feth and Dennard were both graduate students working under Professor Finzi. Dennard’s first project under Feth was the development of fast semiconductor memory based on discrete tunnel or Esaki diodes. The memory’s access time was so fast – 1 nsec – that the memory’s speed far outstripped the logic circuits of the day.

Finally, after working on a variety of projects that produced little more than prototypes and reports, Dennard got the opportunity to join the IBM Research team that was just starting to work on large-scale integrated circuits based on MOSFETs. This work started during a period of time when IBM Research was battling IBM’s Components Division (CD) for control of integrated circuit research within IBM. IBM CD was deeply committed to bipolar IC development, so IBM Research took the opportunity to focus on MOS ICs.

Starting in the mid-1960s, Dennard led a team that was developing IBM’s MOSFET process technology. Early MOS development concentrated on developing a stable MOS process because the first MOSFETs tended to drift quite a bit. One of the group’s milestones was the design of a MOS logic IC with 55 on-chip components. However, memory became the group’s real target because MOS ICs in the 1960s were far too slow to use for logic design.

It was clear that magnetic-core memory was nearing the end of its life. The ferrite cores had gotten about as small as possible while still allowing three wires to pass through the cores’ donut hole. At that time, the focus was on six-transistor static memory cells based on flip-flops, but a chance meeting caused Dennard to think outside of the box.

In late 1966, Dennard attended an internal IBM conference where details of the current IBM Research projects were presented. He was struck by a presentation that described a thin-film magnetic memory that packed hundreds of thousands of bits onto a one-foot-square plate. The simplicity of the memory cell – which consisted of a select wire, a sense wire, and the thin-film magnetic storage medium – appealed to Dennard. (This sounds similar to but clearly different from plated-wire memory.) That night, Dennard pondered the analogy between magnetic and electrostatic storage and hit upon the idea of storing a memory bit as charge on a capacitor, controlled by a single MOSFET to write the bit into the memory cell. It immediately occurred to Dennard that the charge might quickly leak out of the capacitor, given the nature of semiconductors and MOSFETs, but the charge might last long enough to do useful work before the charge on the capacitor needed refreshing.

Dennard did not consider the refresh requirement to be a problem because magnetic-core memories already had destructive readout. At first, Dennard thought that this memory cell might require a second transistor to read out the charge state on the storage capacitor, but he eventually developed a way to read out the state of charge on the capacitor using the same transistor that placed the charge on the capacitor. The one-transistor, one-capacitor (1T1C) DRAM cell was born.

Dennard presented his breakthrough DRAM concept at another IBM Research internal conference, but it appears his presentation got very little attention. Although IBM patented Dennard’s idea for DRAM in 1967, IBM’s MOS process technology was not sufficiently advanced to develop IC DRAMs at the time. Dennard’s DRAM idea went on the shelf.

Instead, Dennard designed a test site chip for a 512-bit MOS SRAM based on six-transistor cells. In IBM terminology, a test site was a partial device designed to prove a concept. In this case, the SRAM test site was a functional chip that implemented one row and one column of the SRAM. The device had a 50nsec access time. Eventually, IBM would fabricate 1Kbit and 2Kbit SRAMs based on this design.

In 1970, Intel introduced the first commercially successful MOS DRAM, the 1103, based on a Honeywell 3-transistor (3T1C) design, and DRAMs quickly replaced magnetic-core memory. Dennard’s 1T1C design would appear in some second-generation DRAMs and became ubiquitous by the time third-generation DRAMs appeared. Although 3T1C DRAM cells have a speed advantage, the cost advantages of a 1T1C DRAM cell are overpoweringly attractive to semiconductor memory makers.

In the early 1970s, Dennard once again found himself at the cutting edge of IC development. A new IBM Research project had set the goal of reducing semiconductor memory costs to one thousandth of a cent per bit, which was several hundred times less than the going rate for memory. It was a very ambitious goal that required working far beyond the leading and bleeding edges of semiconductor lithography at the time, which used 5-micron design rules. Dennard’s team determined that this new goal required 1-micron design rules, which would increase the number of transistors per unit area by a factor of 25. The team needed e-beam lithography to achieve that size reduction. Optical lithography of the day wouldn’t suffice.

This project gave Dennard the opportunity to study the behavior of semiconductors fabricated with device geometries that led the rest of the industry by a decade and a half. That’s when Dennard and his team discovered that circuit behavior – speed and power consumption – would scale favorably with the circuit dimensions. The speed got faster, and the power consumption went down as device geometries shrank and as supply voltages were correspondingly lowered. Dennard and his team summed up his findings in a paper presented at an International Electron Device Meeting in 1972 and then published a more extensive paper in the IEEE Journal of Solid-State Circuits in October 1974. This paper became the ur-document for Dennard Scaling and is the most referenced paper in that journal by a factor of three.

IBM started making DRAMs for use in its own computer systems and Dennard continued to work on DRAMs for many years. In 1979, IBM announced the use of redundant bit lines and word lines to improve DRAM yield. The industry soon followed IBM’s lead. Dennard’s team also continued to work on device scaling, down to 0.1 microns (100 nm) by the year 1995. Moore’s Law gave the semiconductor industry a strong economic incentive to continue its work on shrinking device geometries while Dennard Scaling (sometimes called Dennard’s Law) provided the additional benefits of more performance with lower power consumption with each new process node.

Dennard Scaling became a closely bound corollary to Moore’s Law and, for many people, the two became synonymous. Unfortunately, Dennard Scaling met its end around 2003 with the 90nm process node. At that point, clock frequencies ceased to scale up as fast as they had previously, and power consumption ceased to scale down as fast as in the past. The gains got smaller and smaller as the process nodes progressed, and it takes increasingly more heroic efforts to eke out more speed and lower power consumption as FET geometries continue to shrink. The semiconductor industry enjoyed about 30 years of significant semiconductor progress due to Dennard Scaling, before the laws of physics forced its end. However, Dennard Scaling’s demise does not diminish its historic importance to IC development.

Robert Dennard became an IBM Fellow in 1979 for his outstanding work on MOS technology. Over the years, he received many prestigious awards for his groundbreaking work in semiconductors. These awards include:

1988 – U.S. National Medal of Technology

1997 – Inducted into the National Inventors Hall of Fame

2001 – IEEE Edison Medal

2007 – The Franklin Institute’s Benjamin Franklin Medal in Electrical Engineering

2009 – IEEE Medal of Honor

2009 – U.S. National Academy of Engineering’s Charles Stark Draper Prize for his invention of the DRAM

2010 – Honorary DSc from Carnegie Mellon University

2013 – Inamori Foundation’s Kyoto Prize in Advanced Technology

2019 – SIA’s Robert N. Noyce Award

References

Oral History of Robert Dennard, Computer History Museum, July 20, 2009

J.A.N. Lee, “Robert Dennard,” Computer Pioneers, IEEE Computer Society, 1995

Dennard, et al, “Design of micron MOS switching devices,” 1972 International Electron Devices Meeting

Dennard, et al, “Design of ion-implanted MOSFET’s with very small physical dimensions,” IEEE Journal of Solid-State Circuits, Volume 9, Issue 5, October 1974

Steven Leibson, “A Brief History of the MOS transistor, Part 4: IBM Research, Persistence, and the Technology No One Wanted,” EEJournal, April 17, 2023

Steve Leibson, “Welcome to 3D Week: Why is 3D important? Now? The memory wall, heat, and disposable sensors,” EDA360 Insider, December 12, 2011

Steven H. Leibson, “Decade 90: Advanced ICs portend radical changes in system design,” EDN, March 3, 1988

3 thoughts on “IBM Research Fellow Robert H. Dennard, 1932-2024: Inventor of the DRAM, Formulated MOS Scaling Law”

  1. Atanasoff developed the Atanasoff-Berry Computer (ABC) in the late 1930s and early 1940s. The machine used a capacitive rotating drum to store data. All of Atanasoff’s work predated development of the transistor in 1947 and of the IC in 1959/1960. You could say that Atanasoff was the first to harness capacitive data storage on an electromechanical device, but that’s pretty far from a working DRAM.

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