feature article
Subscribe Now

Group Puzzles Out Silicon Specs

Chiplet Effort Seeks Interface Standards

Someday, a new class of semiconductor companies will assemble their products Lego-style, mixing and matching dice from multiple companies. It’s a huge change that’s still a long way off.

More than 146 people from 80 companies signed up for an event last week at IBM’s Almaden Research Center to take some small steps in this direction. It was the fourth major face-to-face this year for the Open Domain-Specific Architecture (ODSA) group, following others hosted by Samsung and Intel. 

In a sign of growing interest, a similar event a year ago drew fewer than half as many people from fewer than half as many companies. “We don’t know if we have the right solution, but we are reasonably confident we have the right problem,” said Bapi Vinnakota, a silicon architect who leads ODSA.

The problem is that chiplets lack open interoperable interfaces that would enable anyone to assemble them into products. In an effort to create such interfaces, ODSA has started work on physical and link layer specs. It also is designing a board-level proof-of-concept and curating a catalog of existing chiplets, often using proprietary interfaces.

The overall picture from the event was one of an ambitious effort still in its early stages and hungry for engineering and financial resources. A core set of companies, including Globalfoundries, Intel, NXP, Xilinx, and about 20 others are actively participating, but the group needs more help—especially from test vendors and other foundries. 

A PROPRIETARY PAST

The chiplet concept has been around since the multi-chip modules of the 1970’s. Today, the idea is gaining commercial popularity as a way to lower design costs at a time when leading-edge process technologies are become a prohibitively expensive way to design large integrated chips.

For example, AMD built its Ryzen and Epyc x86 processors out of chiplets connected on its Infinity Fabric. Intel is using its EMIB and Foveros packaging techniques to link dice in current and future products. 

Startup zGlue, an active ODSA member, is already offering tools and services for designing modules with chiplets, mainly aimed at the Internet of Things. Its users have several projects in the works the first of which could start shipping to end users next year.

Former Marvell CEO Sehat Sutardja, who attended last week’s ODSA event, was an early promoter of chiplets with his MoChi concept sketched out in a 2015 keynote at ISSCC. At the ODSA event, he informally promoted the latest version of his concept for a final-level cache as an enabler for chiplets.

For its part, IBM described in a talk its Open Memory Interface (OMI) that was announced last month. OMI is a subset of IBM’s OpenCAPI interface aimed at making its server processors more flexible by enabling a market for external memory controllers created by third parties.

IBM is working to get Jedec to create a standard DDR5 DIMM based on OMI. “Open source chiplets could help every company focus on its areas of differentiation,” said Steve Fields, a chief engineer for Power servers.

A WORK-IN-PROGRESS

Plowing its own path, ODSA has an initial list of six publicly available chiplets as a starting point for an online chiplet exchange it wants to create. The short-term goal is to get the industry to start shipping and using chiplets with whatever interfaces vendors want to use, even though they will mainly be proprietary ones.

Toward its long-term goal of creating open interconnects for chiplets, it aims to release at the end of the month a version 0.7 spec for its open physical-layer interface. It is simply called a bunch of wires (BoW). In addition, about a dozen engineers are working to modify existing PIPE interfaces to marry various existing PHYs and link-layer protocols. 

Meanwhile, its proof-of-concept aims to demonstrate the process of how chiplet design would work using existing chips placed on a small printed circuit board with existing interconnects. ODSA is close to a deal to get a limited number of the boards made, although the effort still lacks adequate funding. The boards would give early supporters a vehicle to run and test applications software. 

The board, designed with help from Cisco, consists of a baseboard called Matka and three interchangeable daughtercards called Mara. The Mara cards include one for a Netronome network processor, another for an Achronix FPGA, and a third for a multi-core ARM CPU from NXP. In different combinations, they can enable a smart network-interface adapter or a computational storage processor. Third parties will be able to design their own daughtercards, too.

“We’d love to have people stress our architecture with their software and use cases,” said Quinn Jacobson of Achronix, who leads the team.

The group’s BoW is a 16-wire source-synchronous parallel interface similar to the AIB interface Intel uses in its EMIB package and recently released as open source. It aims to support as much as a Tbit/second of data per millimeter of die edge space at an efficiency of less than a picojoule/bit. Traces could extend up to 50mm, and latencies aim to be as low as 5ns.

“There are multiple proprietary parallel interfaces being built…and an open standard is a great way to converge these designs,” said Mark Kuemerle, who leads the BoW group and is a fellow at Avera Semiconductor, the former Globalfoundries ASIC group now being acquired by Marvell.

The BoW design will allow a variety of bump pitches “but will insist on a bump order to avoid a spaghetti of package routing,” he added.

NEEDS AND HISTORY

The biggest needs for the BoW effort are partners to prototype IP with it and foundries to donate shuttle space for them. Kuemerle also called for help defining the initialization and calibration of the interface, as well as robust test solutions– which he sees as ODSA’s most critical need, overall, at the moment.

“We need input from the test community. We have good ideas that need to be well developed,” he said.

David Kehlet, an Intel engineer overseeing ODSA’s link-layer protocols, called for more work on versions of AXI to accommodate variations among chiplets that will range from RF front ends to memory controllers. “I’ve seen good thoughts on AXI modifications, but nothing available to use,” he said, encouraging open source efforts.

Vinnakota of Netronome and a handful of others published a white paper on the topic of chiplets that sparked the formation of ODSA about year ago. The Open Compute Project (OCP) formed by Facebook agreed to host the project as part of its even broader ambitions to define open versions of everything it needs to build its warehouse-sized data centers.

“We want to get to the point of a completely open system including processors and accelerators,” said Bill Carter, chief technologist of OCP, noting a vision articulated by Aaron Sullivan, now part of Facebook’s semiconductor group for open systems from silicon to racks.

Leave a Reply

featured blogs
Jun 23, 2021
Sr. VP of Engineering Jumana Muwafi explains the role of semiconductor IP development in electronic design automation & shares advice for women in leadership. The post Q&A with Jumana Muwafi, Sr. VP of Engineering: Pushing the Envelope on IP Innovation appeared fir...
Jun 23, 2021
PCB design complexities increase with the increase in the number of parts and layers in a design. For creating these complex designs with maximum efficiency, the design tool should be equipped with... [[ Click on the title to access the full blog on the Cadence Community sit...
Jun 23, 2021
Samtec presented a proof-of-concept demonstration of our new waveguide technology at IMS 2021 in Atlanta, Georgia. In this video, filmed at the show, Mike Dunne, Samtec’s Director of RF Business Development, gives us an update on the new technology and walks us through ...
Jun 21, 2021
By James Paris Last Saturday was my son's birthday and we had many things to… The post Time is money'¦so why waste it on bad data? appeared first on Design with Calibre....

featured video

Kyocera Super Resolution Printer with ARC EV Vision IP

Sponsored by Synopsys

See the amazing image processing features that Kyocera’s TASKalfa 3554ci brings to their customers.

Click here for more information about DesignWare ARC EV Processors for Embedded Vision

featured paper

Create Your Own Custom Chip for Less than $10K

Sponsored by Efabless

Imagine what your team could create if you could develop a custom analog/mixed-signal chip for under $10K. Efabless provides a pre-designed carrier chip which includes a RISC-V processor and subsystem along with ten square millimeters of customizable area, bundled together on a wafer shuttle targeting SkyWater's 130nm process and supported by open-source or proprietary tools for just $9,750.

Click to learn more

featured chalk talk

Build, Deploy and Manage Your FPGA-based IoT Edge Applications

Sponsored by Mouser Electronics and Intel

Designing cloud-connected applications with FPGAs can be a daunting engineering challenge. But, new platforms promise to simplify the process and make cloud-connected IoT design easier than ever. In this episode of Chalk Talk, Amelia Dalton chats with Tak Ikushima of Intel about how a collaboration between Microsoft and Intel is pushing innovation forward with a new FPGA Cloud Connectivity Kit.

Click here for more information about Terasic Technologies FPGA Cloud Connectivity Kit