feature article
Subscribe Now

EFINIX – Yet Another FPGA Company

Novel Devices Target AI, Low Power

We’ve been around the FPGA startup merry-go-round numerous times over the past few decades. It generally does not end well. The usual script goes something like this: brilliant engineers come up with novel ways to make FPGAs smaller, faster, cheaper, more energy efficient, or some combination of those. Brilliant engineers get some venture funding and start working toward first silicon tape-out. Marketing and management folks come on board and start touring the town, PowerPoint in tow, looking for signs of interest from potential customers. Software team works to get a reasonable tool flow up and running.

Years pass.

At least one of the critical items fails to materialize – silicon, software, or customers (usually software, oddly enough). Funding runs out. Everyone goes home. This cycle has repeated over and over. The truth is, it’s really difficult to get a foothold against two entrenched suppliers (Xilinx and Altera for most of history) who are pushing the technology ahead at a breakneck pace with ample silicon development budget, robust and long-proven software tool suites, and armies of talented, knowledgeable applications engineers helping customers succeed.

Now, there’s a new kid on the block, and they appear to be doing things a little differently. Efinix was founded back in 2012… Wait, what?!? That’s not a typo. The company has been quietly working on FPGAs for the past seven years. The founders hail from well-known, successful FPGA companies – Xilinx, Altera, Lattice, QuickLogic, and SiliconBlue, as well as from a number of other marquis semiconductor companies. Investors include Samsung, a handful of Asian venture companies, and… Xilinx? Yep, Xilinx. Apparently folks who understand the FPGA market – both from a technology and business point of view – are deeply involved in Efinix.

Efinix is building their strategy around their Trion FPGAs, with what they call Quantum technology. The company says that Quantum technology delivers a 4X power-performance-area advantage over traditional FPGA technologies. If true, that’s enough to capture our interest. They are applying that advantage to produce a family of programmable logic devices ranging from 4K to 200K logic elements with a small form factor, low power, and pricing aimed at high-volume applications. In other words, targeting the kinds of customers/applications that Xilinx/Intel (Altera) have largely left behind.

Under the hood, Trion FPGAs use a novel logic cell that can be either logic or routing. In conventional FPGA architectures, massive amounts of programmable routing resources are required, and the larger the FPGA the higher the percentage that must be dedicated to routing. In conventional FPGAs, that routing has to be sized to handle “peak” interconnect situations. Otherwise, customers won’t be able to get high utilization of the logic elements, because they won’t be able to route all the required connections. By creating a new type of logic element that can be transformed to either logic or routing, Efinix can make much more optimal use of silicon area. Efinix also says that they can fabricate Trion using only seven metal layers, giving a significant cost advantage over conventional FPGA technologies. Trion is fabricated in SMIC’s 40LL process.

Trion FPGAs also offer optional mask-programmable memory (MPM) to store configuration. With MPM, you can use on-chip MPM instead of an external flash device to configure the FPGA, if you’re looking for the absolute smallest form factor and minimum BOM cost. MPM  requires an NRE charge for the one-time factory programming. After proving your design in regular FPGAs, you submit your design to the factory, and Efinix converts your design into a single configuration mask to be specially fabricated.

Once your system is up and working smoothly with FPGAs, Efinix has another option called “Quantum ASIC” to turn your design “seamlessly” into an ASIC, further reducing cost, improving performance, and reducing power consumption. This is similar to the “HardCopy” option previously offered by Altera, and comparable in some ways to the eASIC technology recently acquired by Intel.

Trion has a range of device sizes and configurations ranging from 4K – 200K logic elements, 4 – 1,760 18×18 multipliers, 77 kb – 14 Mb embedded RAM, DDR3/LPDDR3 up to x64, up to 3x MIPI 4-lane DPHY with built-in CSI-2 controller, and up to 4x PCIe Gen 1 / 2. Packages range from 49-ball FBGA (0.4 mm, 3×3 mm) to 784-ball FBGA (0.8 mm, 23×23 mm), so you can definitely hit the small form factor, if that’s your priority.

On the software tool side, the “Efinity Integrated Development Environment” provides a complete FPGA design suite from RTL to bitstream generation. While many FPGA startups have stubbed their toes on the tool front, it appears that Efinix has at least cleared the first hurdle of enabling customers to bring up reasonable applications using the company’s FPGAs. Since Efinix has set their sights on the low-end FPGA market, they are competing more with companies like Lattice Semiconductor than with Xilinx and Altera, and the development tool requirements are much more relaxed for smaller devices than for the multi-million LUT devices produced by the big two.

Efinix is targeting applications such as machine vision, where cost, power, performance, and form factor are key to winning sockets in devices such as security cameras. As with most of the industry right now, that field is being turned upside down by AI, and Efinix has invested heavily in coaxing strong inferencing performance out of their devices. Last month, the company announced volume production of the Trion T20 FPGAs. The company says they have engaged over 100 customers and are meeting orders for millions of units.

The edge inference market is one of the most aggressively competitive segments these days, so Efinix is likely to have lots of competition. FPGAs have some very attractive abilities in this space, given their flexibility and power efficiency, and Efinix’s ability to roll smoothly into ASIC versions might give them an additional leg up. Still, seasoned competitors such as Lattice Semiconductor appear to be going after the same niche, and a bevy of startups are working on novel architectures targeting the same applications. It will be interesting to watch.

featured blogs
Dec 4, 2023
The OrCAD X and Allegro X 23.1 release comes with a brand-new content delivery application called Cadence Doc Assistant, shortened to Doc Assistant, the next-gen app for content searching, navigation, and presentation. Doc Assistant, with its simplified content classification...
Nov 27, 2023
See how we're harnessing generative AI throughout our suite of EDA tools with Synopsys.AI Copilot, the world's first GenAI capability for chip design.The post Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Power and Performance Analysis of FIR Filters and FFTs on Intel Agilex® 7 FPGAs

Sponsored by Intel

Learn about the Future of Intel Programmable Solutions Group at intel.com/leap. The power and performance efficiency of digital signal processing (DSP) workloads play a significant role in the evolution of modern-day technology. Compare benchmarks of finite impulse response (FIR) filters and fast Fourier transform (FFT) designs on Intel Agilex® 7 FPGAs to publicly available results from AMD’s Versal* FPGAs and artificial intelligence engines.

Read more

featured chalk talk

PIC32CX-BZ2 and WBZ451 Multi-Protocol Wireless MCU Family
Sponsored by Mouser Electronics and Microchip
In this episode of Chalk Talk, Amelia Dalton and Shishir Malav from Microchip explore the benefits of the PIC32CX-BZ2 and WBZ45 Multi-protocol Wireless MCU Family and how it can make IoT design easier than ever before. They investigate the components included in this multi-protocol wireless MCU family, the details of the software architecture included in this solution, and how you can utilize these MCUs in your next design.
May 4, 2023
26,238 views