A few years ago, Lattice Semiconductor was an also-ran in the mainstream FPGA business – lapping up table scraps left by larger competitors Xilinx and Altera. Apparently, that wasn’t all that much fun, so the company set about re-defining themselves as the go-to provider of low-cost, low-power logic devices aimed at high-volume applications. With a smart mix of acquisition and internal development, Lattice created a coherent and compelling product line and, as a result, has shipped over a billion devices in the past four years.

Quietly.

In design after design, Lattice has won the unsung sockets – putting tiny programmable logic chips into novel slots where nothing else would fit. Over time, they’ve captured a solid foothold in areas like system management, security, and edge AI inference, as well as the usual bridge logic situations that have been the bread and butter of FPGA technology since the beginning. Even while surviving a tumultuous failed acquisition, Lattice moved forward with their plan of owning the small FPGA market.

Now, Lattice has a couple of new arrows in their quiver. The company just announced both a new FPGA and a major upgrade to their “SensAI” edge inference stack. The two new offerings hit squarely in Lattice’s sweet spot and should gain them additional traction in the IoT market for low-cost programmable logic. The company is hitting at two of the most critical aspects of connected system design at the edge these days – securing applications and enabling AI inference at the edge – and they have a decent head start on what is definitely becoming a highly competitive segment.

The new MachXO3D devices are designed specifically to provide hardware root-of-trust capability for embedded systems in a wide range of industries including consumer, medical, industrial, automotive, networking, and broadcast. The company takes a holistic view of security challenges and works to address them throughout the lifecycle – including not just “in the field” threats, but from design and manufacturing through transport, installation, operation, and end-of-life. For many companies with non-captive manufacturing, for example, counterfied and overbuilding are major security issues. The capabilities in MachXO3D are designed to span the entire gamut of threats.

The idea behind hardware root-of-trust is that the security device is the first device powered on and the last device powered off, and allows the system to verify its own code and configuration based on a hardware-implemented security mechanism.

As such, it is designed to be a foundation for system trust. Lattice says MachXO3D is the industry’s first control-oriented FPGA compliant with new NIST SP 800 193 Platform Firmware Resiliency (PFR) guidelines. The philosophy is to protect against attacks, detect malicious code, and recover in case of corruption. MachXO3 protects non-volatile memory through access control, cryptographically detects and prevents boot from malicious code, and recovers to latest trusted firmware in case of corruption.

The FPGA architecture allows ports to be dynamically re-configured at any time to minimize the attack surface and provides the ability to dynamically change the instruction set and security scheme (all within a field-deployed system). The scheme appeals to everything from small-scale embedded systems to heavy-iron servers. The company says that “5+ server OEMs” are currently working on designs secured by MachXO3D.

Under the hood, MachXO3D has added a set of hardened pre-verified security functions to their existing FPGA architecture. These include a unique secure ID for the device itself, a true random number generator, SHA256/HMAC service, ECIES/ECDH service, AES256/128 encryption/decryption, public/private key pair generation, and ECDSA256 authentication and signature generation service. In addition, they have added a second secure configuration storage, which is designed to improve update reliability by allowing failover to the “last good” or “golden” bitstream image. There is also a hardened configuration engine that boots only from authenticated bitstreams. All of this is in addition to the existing MachXO3 FPGA features.

Moving from security to the wild wild world of AI inference at the edge, Lattice is also announcing a major upgrade to their sensAI stack for super-low-power always-on edge-based AI inference. Lattice was very early to the edge-based AI game, and the company has cleverly set their sights modestly on the scope of AI challenges they tackle with their devices. As a result, they have technology that is unmatched in the area of always-on and low power. By focusing on problems such as presence detection, object detection and counting, they can solve a huge number of problems on their own, as well as acting as a gatekeeper when higher-power engines need to be brought online. For example, human presence detection is a key end result in many systems, but if additional inference processing is desired beyond simple “detection,” Lattice’s AI could act as the gate keeper, powering up the larger, more power-hungry inference engines only when there is a human in view to analyze. Lattice: “Someone is here.” Big Inference Engine: “Ah, it’s Joe.”

The current announcement is basically a 10x performance boost – achieved on top of their existing sensAI stack. The underlying hardware can be tiny iCE40 UltraPlus FPGAs, for minimal applications like presence detection or gesture recognition, or much more powerful ECP5 FPGAs for video interface and processing. On top of those devices, the stack includes neural network accelerator core IP – a “CNN compact accelerator” and a “CNN accelerator” – for the two FPGA families. On top of that IP, there is a software layer that provides a path from neural network compilers such as TensorFlow, Caffe, and Keras – through Lattice’s own FPGA tools. Then, the icing on the AI cake is a set of reference designs and demos for applications such as face detection, hand gesture detection, key phrase detection, human presence detection, face tracking, object counting, and speed sign detection. Finally, the company offers custom design services for those who want to accelerate the AI portion of their system design without adding additional engineering expertise.

As examples of the new 10x performance boost, Lattice offers demos such as human presence detection with a CMOS image sensor – 64x64x3 resolution at 5 frames per second – consuming a downright miserly 7 mW in an iCE40 UltraPlus device. And, on the other end of the spectrum, human counting with a CMOS image sensor at 128x128x3 resolution at 30 fps, using 850 mW on an ECP5-85K device. These power consumption rates are incredibly low for these tasks and would be extremely challenging to meet with any other technology.

It has been interesting to watch Lattice essentially create a new market for super-small, super-inexpensive, high-performance FPGAs. When they launched their first campaign years ago with a tagline “World’s Smallest FPGAs,” at a time when the entire FPGA industry was built around the “my FPGA is bigger than yours” philosophy, we knew that Lattice had made a major pivot. It appears that pivot is now paying off.