They say you don’t often get second chances. Certainly, there are few examples in the technology world where an entire industry blows a big market opportunity, backs away, and then gets another crack at it later. But, that could possibly happen with EDA and FPGAs. We might be on the verge of a time when the EDA industry could patch the big hole in their collective system design dike and take full control of the electronic design process once again.

About two decades ago, the EDA industry became keenly interested in the emergence of FPGA technology. It was a pivotal time for FPGAs, as the complexity of the biggest devices was just becoming too much for the simplistic schematic capture through place-and-route design flow that characterized the early days of programmable logic. This was the time for EDA to make its move, with existing established design flows for language-based design.

The big three EDA suppliers answered the call, along with a bevy of EDA startups. Before you knew it, there were RTL simulators, code checking tools, RTL synthesis tools, physical synthesis tools, floor planners, system design tools, pin mapping and IO assignment tools, embedded debuggers, DSP design tools, and even early high-level synthesis tools targeting FPGAs from a variety of third-party EDA suppliers. EDA companies touted “vendor independent” design flows that would allow design teams to buy a single set of tools and master one flow, and then apply that process across FPGAs from multiple FPGA companies. Tools would come from EDA; silicon and support would come from FPGA vendors. It was a great story, and it left EDA in the driver’s seat as the industry that provides tools and IP.

It totally did not work.

FPGA companies didn’t really like the idea of leveling the playing field. They didn’t want to give up control. But at that point in time, they needed technology that was unique to the EDA industry. FPGA companies didn’t have robust synthesis or simulation tools to offer. They did have one ace in the hole, however: The only place you could get place-and-route software for FPGAs was from the FPGA companies themselves.

With FPGA companies having a lock on place-and-route, EDA was blocked from building a complete design flow. You could work all the way through synthesis with EDA tools and get some estimates about how your design would perform, but until you ran the FPGA company’s place-and-route tool, it was all just a guess. And, when geometries got small enough that place-and-route data was critical for timing closure, EDA didn’t have access to the information they needed to properly implement the design upstream.

At this point, we had a standoff. Neither EDA nor FPGA could own the complete design flow. Both EDA and FPGA had intense rivalries within their own segments. There was a deadlock on FPGA design tools, and something had to give.

Then, EDA made a fatal error – they blinked first.

It was the fault of the EDA sales channels, really. EDA primarily relied on a “major accounts” strategy, with entire sales teams assigned to giant corporate customers and huge multi-year “all-you-can-eat” deals driving the majority of EDA revenue. EDA was not equipped to service the breadth and size of the FPGA market. EDA companies got most of their revenue from a couple dozen big customers. FPGA companies’ customers numbered in the tens of thousands. In coming to grips with that problem, somebody got a brilliant idea – “Let’s OEM EDA tools through FPGA vendors!”

The OEM idea was seductive to EDA marketers. Rather than trying to find a way to sell to the broad FPGA market, they could piggy-back on the FPGA companies’ sales channels. EDA would supply the tools to the FPGA companies, the FPGA companies would integrate and bundle them with their own tools and supply them to the end customers. EDA just needed to sit back and collect the big quarterly checks.

The problem was, there was an intense rivalry in FPGAs between Xilinx and Altera, and neither of those two players could afford to be behind in the tools race. They also couldn’t afford to let the price of tools be a barrier to design wins and silicon sales. They needed customers to have easy access to cheap, robust tool flows so that designs could be finished and silicon could be sold. The obvious solution? Subsidize the tools and reduce the price to the end user. And, since neither Xilinx nor Altera could afford to let the other offer cheaper tools, a race to the bottom quickly dropped the price and perceived value of FPGA tools to “free.”

It’s hard to make a living selling free stuff. EDA companies switched to a strategy of offering upgrades to the FPGA vendors’ tool suites, but the price tags of the EDA tools (compared with the “free” of the FPGA vendor tools) made the upgrade a tough sell. At the same time, FPGA companies began a slow but steady effort to rid themselves of the EDA OEM tools. One at a time, they built their own tools to replace those they were getting from EDA. These new tools were not in a league with the EDA tools, of course. But FPGA vendors had the tactical advantage. They offered their own tools for free, and left the more-capable EDA tools as extra-cost upgrades. This let them snag the low end of the market for themselves, while still allowing their key customers access to the good stuff.

Gradually the FPGA tools got better. Gradually the EDA tools generated less revenue and stagnated. It was hard to compete with “free,” even when you were selling high-quality tools. The FPGA companies hired expert engineers from EDA and evolved their own tools rapidly. Eventually, the FPGA tools caught up with the EDA tools, and the market for third-party EDA software for FPGA design dried up. The FPGA companies had won.

The EDA companies sought refuge in their happy place – custom IC design. They redeployed their FPGA tools and IP to support FPGA-based prototyping and emulation flows. ASIC and ASSP companies had huge budgets for tools, particularly when it came to verification. EDA could sell to their normal channel to their normal customers. Life was simple once again.

Now, there is a new possibility on the horizon. At least two companies now offer FPGA fabric as IP, allowing ASIC and ASSP design teams to embed programmable logic directly into their custom chips. This is important because it breaks the monopoly (duopoly, actually) on programmable logic for system designers. In the past, programmable logic was mostly an alternative to hard-wired logic. It was good for prototyping, or for new standards or applications where application-specific custom chips were not yet available. Now, however, programmable hardware is a requirement for high-demand applications such as data center acceleration, deep learning, and embedded vision.

With embedded FPGA IP, there is now an alternative to buying that required programmable part of your design from an FPGA company. ASIC and ASSP design teams can include programmable logic fabric on the same chip along with their other custom circuitry – rather than having to park an FPGA next door. It potentially allows third parties to produce more targeted SoCs than those available from FPGA companies.

All they need is good tools.

And, they don’t need good tools only for themselves. They potentially need them for the end users of their devices. If an ASSP company produces a chip that includes some programmable logic component that is customized by the end user, that ASSP company needs to be able to provide a robust tool suite that can make the FPGA part work.

While the tool offerings from the current embedded FPGA companies (Achronix and Flex Logix) appear to be decent, they probably can’t compete with the high-end technology that EDA companies have in house. This is EDA’s second chance. By partnering with (or acquiring) companies in the embedded FPGA space, they could re-take the offensive in programmable logic. They could have end-to-end solutions including tools and IP for companies developing ASICs and ASSPs to tackle some of the most challenging high-value application problems that exist today.

Clearly, FPGA companies want to own the market for “programmability.” They have spent decades putting themselves in a position where they control the IP and tools required to make the magic of programmability happen. Their defenses are formidable, but it is possible that the right combination of tool and IP technology could span their moat. It will be interesting to watch.