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Achronix Goes Head-to-Head

Taking Their Bite out of the Middle

For leading FPGA suppliers Xilinx and Intel (Altera), the secret to success has always been to beat the other. That’s how duopolies work. For everyone else wanting to wedge their way into the highly-competitive programmable logic market, common wisdom has always been to find a niche. 

The niche strategy is more of a survival trick. Numerous companies have made a decent living by zooming in on just one aspect of the FPGA market – military/aerospace applications, ultra-low power applications, small form factor, and so on. Companies chose their niche, focused their R&D and marketing efforts at wooing those customers, and steered well clear of the mainstream high-end FPGA market that forms the bread and butter of the two big suppliers.

Achronix decided to take their niche right out of the middle.

And, it has worked. Achronix is now well past the “startup” stage (going on sixteen years now), is preparing for an IPO, and has a formidable presence directly in the largest and most valuable markets for Xilinx and Intel. It’s an achievement unmatched by any other FPGA company in the modern era.

Achronix essentially spun the niche strategy on its head. Rather than finding a market that the two big players have ignored, they focused on the mother lode – the high-end FPGA market that represents the largest segment of the FPGA business. Where the two big players design in features and make compromises that are aimed at making their big devices applicable to a wider audience, Achronix focused only on one-upping them in the most valuable one – the heart of their business. That means they were able to optimize a few things the other folks were not, and, for many customers, that produces a differentiated solution.

Achronix’s marketing slides look surprisingly similar to those of the X/I duo. They are going after 5G infrastructure, automotive, AI/ML, compute acceleration, computational storage, defense and hardware assurance, networking, and test and measurement. And, they are going directly after the same sockets in those applications as the big guys, not building a friendly comic side-kick to sit alongside the “main” FPGA. 

Xilinx and Intel both say they don’t often encounter Achronix competitively. A large set of very important Achronix customers would beg to differ. OK, actually they wouldn’t “beg.” They’d be more likely to just sit quietly with Achronix designed into their systems hoping competitors don’t notice where they gained some advantage.

Starting with stand-alone FPGAs themselves, Achronix is currently shipping their Speedster 7t FPGAs, which are formidable high-end devices by anyone’s standard. Speedster 7t, as you might guess from the name, is fabricated on TSMC 7nm technology, and it includes high-speed transceivers, namely up to 112 Gbps SerDes and 400G Ethernet and PCIe Gen5 interfaces. This puts them at parity or better on the business of getting massive amounts of data on and off the chip quickly. They also took a page from Xilinx’s book (and apparently one-upped them a bit) by including a high-performance network-on-chip (NOC), with an eye-watering >20Tbps bandwidth. 

Those familiar with the challenge of achieving timing closure on large FPGA designs know that, beyond a certain density, it becomes almost impossible to synthesize and place and route your circuit and meet all your timing constraints. Routing congestion on traditional FPGA fabric just becomes too big an issue, and the computation required to optimize such large designs is staggering. While FPGA companies have labored for years to improve the performance and capacity of their design tools, Moore’s Law was unrelenting. Somehow, an architectural change was needed. 

Historically, Intel blinked first – taking a page from the early Achronix playbook. Achronix’s original FPGA design (back in the day) was asynchronous, using a series of tiny registers scattered around the chip to retime the design and eliminate long critical timing paths. Altera (before being acquired by Intel) came up with a surprisingly-similar architecture they call “Hyperflex” which allows the design tools to split up long paths with registers, reducing the need to optimize for long runs. 

Xilinx and Achronix both went the NoC route (we don’t know who came up with the idea first, but Xilinx was the first to announce). The NoC takes over long-run, high-bandwidth on-chip data connections, dramatically reducing the load on regular routing and reducing the need for optimization in synthesis and place-and-route. Achronix claims their NoC is significantly faster than Xilinx’s, although we haven’t seen definitive benchmarking to establish Xilinx’s speed.

Achronix also overhauled their DSP block strategy, optimizing specifically for AI/ML inference with their machine-learning processors (MLPs). These include fully-fracturable integer MACs that operate up to 750MHz with their own integrated memory. This approach differs from Xilinx’s AI engines on their Versal devices, and, here again, we don’t have definitive data to prove which is better.

Speaking of memory, Achronix made a bold strategy decision to equip Speedster 7t with eight hardened GDDR6 memory interfaces, giving a total memory bandwidth of 4 Tbps. This provides high-bandwidth memory performance comparable to the HBM offered by the other two competitors, but with more readily available components, and without requiring interposer-based design. 

Collectively, these features make Speedster 7t highly competitive with Xilinx’s Versal and Intel’s Agilex offerings for many important applications. But part of Achronix’s cleverness is in the design life-cycle department. For many of the target application areas – 5G being a great example – teams want to get to market as fast as possible, and then come back later and cost-reduce. The typical strategy is to do the first generation design with FPGAs carrying the heavy loads, and then come back and re-engineer those designs with custom ASICs to reduce cost, reduce power, and improve performance. But, with many modern designs, programmability is a key functional requirement, not just a prototyping feature. That means that FPGAs are likely to have a longer lifespan in those sockets, and replacing them with ASICs is more challenging and expensive. Additionally, new techniques such as system-in-package design promise to blur the line between FPGA- and ASIC-based versions of designs, allowing incremental hardening and optimizing while maintaining the flexibility offered by FPGAs. 

Achronix is unique in this market by offering “Speedcore” eFPGA IP that matches their stand-alone FPGAs. That means you can start your system with a Speedster device, and then use the eFPGA IP to design your own chip that integrates your Speedster design with application-specific hard blocks to create an ASIC that brings the best of both worlds. Neither Xilinx nor Intel has taken this step, and it should make Achronix appealing to a class of customer for whom custom ASIC design is a key strategy.

On the other end of the spectrum, Achronix also offers a “solution” version of their technology with their VectorPath Accelerator Card. This is a strategy currently being pursued aggressively by both Xilinx and Intel as they go after the mainstream data center acceleration business, so it helps to level the playing field for Achronix in that arena as well.

It will be interesting to watch the competition unfold, now that all three vendors of high-end FPGAs are shipping comparable devices in production. Development teams are definitely the winners, as each company is bringing unique ideas and strategies to market that may prove valuable to one application or another.

One thought on “Achronix Goes Head-to-Head”

  1. Failure to note that 99% of Achronix’s revenue comes from Intel is a big omission in this story, as is the failure to note that they’re just about to complete their Spac merger just as said revenue stream is nearing it’s end.

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