feature article
Subscribe Now

A New Standard for FPGA Peripherals

Opal Kelly Announces SYZYGY

FPGA boards are quite possibly the most versatile and useful tools in our engineering hardware toolboxes. A competent hardware engineer can grab an FPGA board and pretty quickly solve a wide variety of problems and challenges. Need to accelerate an algorithm in hardware? Want to process data coming in from high-speed peripherals? Have some interconnect, buffering, sensor fusion, or other challenging interface problem? An FPGA board will probably get you to a working solution faster than just about anything.

But virtually nobody uses FPGA boards in isolation. Invariably, we need to connect peripherals – cameras, sensors – the list goes on and on. Also, invariably, hooking those boards up to our FPGA-based system is one of the most challenging and time-consuming tasks in our build-out. Nobody wants to design a custom interface, so we turn to standards whenever possible. For FPGAs, the most popular and versatile interface standard is FMC (FPGA Mezzanine Card). FMC defines a plug and socket that basically externalize all the pins of the FPGA, so that designers of peripheral boards can build in a standard plug that will get them the signals they need. FMC is a robust standard that has evolved over the years as pin counts have risen, IO speeds have increased, and SerDes transceivers have become more common.

The downside of FMC is the cost, complexity, and size. FMC plugs and sockets are large and expensive, limiting the form-factor of your board and adding a big chunk of cost to your finished product. For many applications – in fact for most applications – FMC ends up being some measure of overkill. Lots of those pins and sockets sit idle, wasting valuable space, cost, and IO that might be used for other things. In many simple applications, builders of peripheral boards and modules opt for simpler, lower-cost standards such as Diligent PMOD. For low-speed, cost- and form-sensitive applications, PMOD provides a nice, simple alternative to FMC, enabling the peripheral cost to drop down into the single-to-low-double-digit range, versus solid triple-digit to four-digit price tags for typical FMC-based peripherals.

There’s a huge gap between the 6- or 12-pin simplicity of PMOD and the 72- or 200-pin multi-gigabit world of FMC, however. And no current standard does a good job of filling the gap between those poles… until now, at least. Opal Kelly, a leading producer of FPGA modules, has defined a new standard called SYZYGY, and it is offering it as an open standard for connecting high-performance peripherals to FPGA systems. For many applications, SYZYGY should hit a sweet spot that saves considerable cost and space compared to FMC.

The goals with SYZYGY were to provide broad peripheral support, with high speed single-ended as well as differential interface standards, to maintain FPGA pin economy by offering a moderate pin count for small, single-purpose peripherals, and to keep overall solution cost significantly lower than FMC. In addition, Opal Kelly wanted to provide programmable power delivery with SmartVIO for flexible FPGA IO voltages, and to enable the use of low-cost, high-performance cabling where required. 

SYZYGY comes in two flavors – one with support for multi-gigabit transceivers (cleverly called “SYZYGY Transceiver”) and one without (“SYZYGY Standard”). This is a smart compromise, and it sets SYZYGY apart from FMC’s one-connector-fits-all approach. For designs that don’t require transceivers,  the cost and complexity would be increased significantly with a one-connector solution, so SYZYGY Standard allows non-transceiver applications to keep cost and complexity low, while maximizing pin utilization in a small form factor. 

SYZYGY Standard uses a Samtec 40-pin QTE/QSE mating connector pair with an 0.8mm pitch with impedance control, and an optional latching connector capability. It supports 28 single-ended IOs, 8 pairs of which are differential capable. SmartVIO allows FPGA IOs to be programmed for 1.0V to 3.3V at 2A, in 10mV increments. I2C is used for personality and control of SmartVIO. SYZYGY Standard supports speeds up to approximately 500 Mpbs/pin (so 1Gbps for differential pairs). 

If cabling is needed, SYZYGY Standard uses a Samtec EQCD-020, which provides performance of 11 Gbps for a 10” cable. The cable has an optional screw mount on both ends and is an impedance-controlled, shielded coaxial cable. The Samtec EQCD-020 prices in at a thrifty $21 (for 100pc, 6” cable), which, along with the low cost of the connectors, can dramatically reduce your BOM cost compared with FMC.

For applications that need transceivers, SYZYGY Transceiver provides high-performance transceiver connections and maintains the small form factor and low cost with a reduced number of standard IO pins. SYZYGY Transceiver uses a Samtec 40-pin QTH-DP/QSH-DP mating connector. This connector has a 0.5mm pin pitch, and it is optimized for differential signals with extra separation between differential pairs. Like the Standard connector, the Transceiver connector also offers an optional latching connector capability. SYZYGY Transceiver supports 18 single-ended IO plus two Tx and two Rx lanes for transceivers. It uses the same I2C for personality and SmartVIO control as SYZYGY Standard, and it offers performance of 500 Mbps/pin for the single-ended IO and up to 10 Gbps for each of the two transceiver channels.

A cabling solution is offered for the Transceiver version as well – the Samtec HQDP-020 – which is a twinaxial differential cable providing up to 19Gbps for a 10” cable with optional screw mount on both ends. The price comes in at a shockingly low $66 at 100pc of 6” cable, which is truly remarkable for a cabling solution with multi-gigabit performance in such widths. Here again, a SYZYGY Transceiver-based design would come in at significantly lower cost and smaller form factor than the same design with FMC.

Opal Kelly is seeding the SYZYGY standards universe with the offering of an open-source FPGA SYZYGY-compatible carrier. The carrier is based on the Xilinx ZYNQ device, and it includes three SYZYGY Standard ports and one SYZYGY Transceiver port, SmartVIO power delivery, 1-Gb Ethernet, 1GiB DDR3-800, USB Type-C (host and device modes), USB Serial UART (console access), Linux OS, and 5V to 18V power input.

In addition to the open-source carrier, Opal Kelly is launching a versatile set of peripherals that conform to the SYZYGY standards, including two analog-to-digital converters (one based on the Linear Technology LTC2264 and one based on the Analog Devices AD9116), an image sensor (based on the ON Semiconductor AR0330), a Diligent PMOD expansion, and a Small Form-Factor Pluggable Transceiver.

The LTC2264 A/D converter peripheral is based on SYZYGY Standard, and it offers 125 MBPS at 12-bit resolution. It has transformer-coupled or op-amp-buffered output, dual channel simultaneous sampling, and edge-launched SMA inputs. The AD9116 A/D converter offers similar performance and features, but with only transformer-coupled output, an optional external clock input, and dual-channel simultaneous sampling. The AR0330 image sensor peripheral is also a SYZYGY Standard peripheral with a 3.4 megapixel CMOS digital image sensor, providing 60 fps at 1080p and high-speed capture of 215 fps at 640×480 resolution.

The PMOD expansion peripheral is a SYZYGY Standard peripheral that breaks out the SYZYGY connection into four Diligent PMOD ports. This breakout board makes it so that a SYZYGY carrier board could be easily paired with a variety of existing PMOD-based peripherals. The PMOD expansion peripheral features a double-wide cable arrangement for maximum flexibility.

The Small Form-Factor Pluggable Transceiver (SFP) Peripheral is (of course) based on the SYZYGY Transceiver standard, and it provides dual SFP cages that accept standard SFP+ modules. The SFP peripheral supports up to 10Gbps signaling, and it opens up the SYZYGY universe to a wide range of existing SFP+ devices. 

The world of “proprietary standards” (open standards created and offered by commercial interests) can be confusing. Opal Kelly owns the SYZYGY mark, and licensees (both carrier manufacturers and peripheral manufacturers) may use the mark free of charge as long as their products fully comply with the SYZYGY specification. Licensees provide a “compatibility table” showing what their device is meant to work with, and then they may use the term “SYZYGYtm Compatible” referring to their offering. Opal Kelly offers SYZYGY licensing for free in order to encourage industry-wide proliferation and adoption.

From our perspective, SYZYGY fills a wide gap in the FPGA standards universe, and it should be attractive to a diverse set of peripheral suppliers as well as carrier board manufacturers. SYZYGY offers a much lower-cost, smaller form-factor alternative to the weighty FMC, with a reasonable subset of the capability that should be compelling for a wide range of applications. It will be interesting to see how SYZYGY is received by the FPGA industry at large.

3 thoughts on “A New Standard for FPGA Peripherals”

  1. No mention of HSMC?

    Also, is it EEJournal policy to not have images in articles? Would have been nice to see the connector or at least source links so I don’t have to manually search for it.

    1. @jojo64, Ah, you got me on HSMC! It should have been in there. We were talking primarily about Xilinx-compatible boards, so HSMC slipped my mind.
      Regarding photos – good point. We’ll try to add some.
      Thanks for the feedback!

Leave a Reply

featured blogs
Aug 7, 2020
I love the clickety-clackety sounds of split flap displays, but -- in the case of this kinetic clock -- I'€™m enthralled by its sedately silent revolutions and evolutions....
Aug 7, 2020
HPC. FinTech. Machine Learning. Network Acceleration. These and many other emerging applications are stressing data center networks. Data center architectures evolve to ensure optimal resource utilization and allocation. PECFF (PCIe® Enclosure Compatible Form Factor) was dev...
Aug 7, 2020
[From the last episode: We looked at activation and what they'€™re for.] We'€™ve talked about the structure of machine-learning (ML) models and much of the hardware and math needed to do ML work. But there are some practical considerations that mean we may not directly us...
Aug 7, 2020
This is my second update post where I cover things that I have covered before, and where there is some news, but no enough to make a completely new post. The first update was Weekend Update .... [[ Click on the title to access the full blog on the Cadence Community site. ]]...

featured video

Product Update: High-Performance DesignWare Memory Interface IP

Sponsored by Synopsys

Get the latest update on Synopsys' DesignWare Memory Interface IP for DDR5, LPDDR5, and HBM2/2E and how you can enable your DRAMs with the highest-performance, lowest-power, and lowest-area IP solution.

Click here to learn more about Synopsys' DesignWare Memory Interface IP for DDR5, LPDDR5, and HBM2/2E

Featured Paper

Improving Performance in High-Voltage Systems With Zero-Drift Hall-Effect Current Sensing

Sponsored by Texas Instruments

Learn how major industry trends are driving demands for isolated current sensing, and how new zero-drift Hall-effect current sensors can improve isolation and measurement drift while simplifying the design process.

Click here for more information

Featured Chalk Talk

Wide Band Gap: Silicon Carbide

Sponsored by Mouser Electronics and ON Semiconductor

Wide bandgap materials such as silicon carbide are revolutionizing the power industry. From electric vehicles and charging stations to solar power to industrial power supplies, wide bandgap brings efficiency, improved thermal performance, size reduction, and more. In this episode of Chalk Talk, Amelia Dalton chats with Brandon Becker from ON Semiconductor about the advantages of silicon carbide diodes and MOSFETs.

Click here for more information about ON Semiconductor Wide Bandgap SiC Devices