feature article
Subscribe Now

The Big Dog

Peace and Love and Universal Verification

Dogs need to know who’s on top. They don’t always have to be on top, but they get completely stressed out when they don’t know who is. When a dog with naturally aggressive (or at least assertive) tendencies enters a strange situation, it will act as if it’s in charge. And if nobody objects, then, by gum, it is in charge. If someone objects, well, then a score must be settled, and the newcomer may just have to back down.

And this is often how it works with de facto standards: in order to be the “unified” or “universal” standard, simply declare yourself to be that. If no one objects, then Bingo! You are in fact the universal or unified solution.

Count the number of “universal” solutions you’ve seen. Now count how many are actually considered universal by those competing with the company declaring universality. That percentage is probably reasonably small.

So it bears noting, then, that there is something new in the universe that appears to be truly universal. Foes are cooperating and sharing code. Lambs lie with lions and mice with elephants. Presumably, once any resulting tools are released, there will be some magic key combination you can type that will throw you into a hidden flight simulator, and your speakers will utter, in a mellifluous mezzo voice, “In the unlikely event of a water landing, we shall all join hands and sing Kumbayah.”

When the likes of Synopsys and Cadence climb into bed together to share deep secrets, inviting Mentor to join in, well, it gives one cause for pause. And you know that either they have to be solving something that’s really annoying for all three of them, or… perhaps their customers shouted really loudly.

The upcoming collaboration is the Universal Verification Methodology (UVM), an effort underway in the Accellera standards organization. It combines elements of both VMM and OVM, although which of these predominates depends on your point of origin.

SystemVerilog has been a boon for verification, but, as Synopsys’s Swami Venkat describes it, it was too big and unwieldy, and customers asked for more guidance on how to manage a methodology with it. Synopsys’s solution was the Verification Methodology Manual (VMM; they seem fond of methodology manuals there).

Meanwhile, Cadence and Mentor banded together to create the open-source Open Verification Methodology (OVM). And the stage was set for the classic EDA two-standard conflict. Synopsys tools worked with VMM, and Cadence and Mentor tools worked with OVM. And of course, everyone else caught in between somehow had to satisfy both (unless their tea-leaf-readers could divine an eventual winner), and customers ended up with disjoint pieces of verification paraphernalia that couldn’t interoperate.

Verification IP was apparently the biggest bone of contention here, and Accellera initially took up the issue of facilitating VIP interoperability. If you look at an old 2008 OVMWorld blog posting, a Mentor poster takes pains to clarify that “The charter of the [technical sub-committee] is to develop a scheme for VIP interoperability, NOT to define a common base-class library…” unless the Board changes its mind.

Apparently, having launched the VIP Interoperability Layer, the Board changed its mind. In the words of Accellera’s Shrenik Mehta, “Documentation is not enough.” So what’s being readied at the moment is in fact the first fruits of an effort to provide base classes. From the standpoint of a standards body, this is a bit novel since they’re not just providing a standard; they’re actually providing code. Mr. Mehta clarifies that it’s not actually a new thing for them: they already provided an Open Verification Checker Library. So, while perhaps unusual, it’s not unprecedented.

The foundation underlying UVM will depend on whom you talk to – even though they’re cooperating, no one has hidden their company badge. Mentor’s John Lenyo and Cadence’s Tom Anderson talk in terms of UVM being based on OVM. Meanwhile, Synopsys talks about their Janick Bergeron having donated most of the “seed implementation.” But, such niggling points aside, all agree on the following: UVM more or less started by combining OVM and VMM and then deprecating things that weren’t good and adding things that were missing.

So, specifically, UVM will not be backwards compatible with either OVM or VMM. Such backwards compatibility is still considered a nice thing to attempt, but where “doing the right thing” conflicts with it, the “right thing” trumps.

As to the process of creating base classes, this is not something that the Accellera organization is doing as a specifically-funded activity with its own engineers. The member companies donate and vet code, and support is managed as with other open source projects.

It starts with committee volunteers signing up to write a spec for various features. Sometimes competing specs will show up and the committee resolves the differences into a single agreed-on spec. At that point, no code has been written, except perhaps to demonstrate that some element of a spec can be implemented.

Given the agreed-upon spec, it can then be implemented. Again, members can go off and write code. When the code comes back, the committee can review and test it. The results, once fixed up, can then be released as open source.

The first set of these classes was released to “early adopters” on May 17, 2010. According to Accellera’s Yatin Trivedi, the purpose is to get user input and test the waters by focusing on three features: call-backs, end of test, and message catching. This will help get input from the verification community on the value of UVM and the next steps to be taken. Assuming the community approves, development will be an ongoing activity. Which, of course, means that the current momentum of volunteer work needs to be sustained for the time it will take to complete all of the work.

Evidence of this outbreak of universal love and understanding can be found at an upcoming breakfast panel at DAC in Anaheim on June 15. There Accellera, Freescale, Intel, Cadence, Mentor, Synopsys, and Xilinx will vie for primacy demonstrate their spirit of cooperation and collaboration in touting the upcoming product of their enduring harmony.

And for now they seem happy enough living with the ambiguity of not having an alpha in charge. You could question whether dogs are the right metaphor, but they’re not acting like cats, since some coherent group instincts prevail, yet not to the extent of sheep. So we’ll stick with dogs in an uneasy pack. Where no one but the standard gets to be the Big Dog.

More info: Accellera VIP Activity

Leave a Reply

featured blogs
Nov 12, 2024
The release of Matter 1.4 brings feature updates like long idle time, Matter-certified HRAP devices, improved ecosystem support, and new Matter device types....
Nov 7, 2024
I don't know about you, but I would LOVE to build one of those rock, paper, scissors-playing robots....

featured video

Introducing FPGAi – Innovations Unlocked by AI-enabled FPGAs

Sponsored by Intel

Altera Innovators Day presentation by Ilya Ganusov showing the advantages of FPGAs for implementing AI-based Systems. See additional videos on AI and other Altera Innovators Day in Altera’s YouTube channel playlists.

Learn more about FPGAs for Artificial Intelligence here

featured paper

Quantized Neural Networks for FPGA Inference

Sponsored by Intel

Implementing a low precision network in FPGA hardware for efficient inferencing provides numerous advantages when it comes to meeting demanding specifications. The increased flexibility allows optimization of throughput, overall power consumption, resource usage, device size, TOPs/watt, and deterministic latency. These are important benefits where scaling and efficiency are inherent requirements of the application.

Click to read more

featured chalk talk

MEG-Array and M Series
Sponsored by Mouser Electronics and Amphenol
In this episode of Chalk Talk, Jeremy Ellis from Amphenol Communications Solutions and Amelia Dalton chat about the benefits of Amphenol’s MEG-Array and M-Series connector solutions. They also investigate the tooling configurations available for these solutions and how Amphenol’s ball and socket BGA interface can simplify board routing, eliminate press-fit constraints on via and provide excellent SI performance.
Oct 21, 2024
25,724 views