A few weeks ago, if I had heard of the RISC-V Instruction Set Architecture (ISA), it was only in passing. How things have changed. Kevin Morris has covered the announcement that RISC-V IP is available for a wide range of Microsemi’s FPGAs. Around the 5th RISC-V workshop in November, there was a flurry of announcements. At several meetings and conferences I have attended, RISC-V has been discussed in the informal sessions. And now there are rumours in various places on the Internet that Samsung is planning a device using RISC-V.
So what is it, and why is there a buzz now?
An ISA is the list of commands that I have seen defined as where the software meets the hardware; a processor can be seen as the physical implementation of the ISA, and radically different hardware can execute the same instruction set. (Historical note – this is how AMD processors can run the same instruction set as Intel processors without incurring court cases.)
RISC (Reduced Instruction Set Computing) has been around a long time. It began in universities in the 1980s: Stanford’s work begat the MIPS architecture, which is now owned by Imagination Technologies, and, across the Bay at Berkeley, they created what became the SPARK architecture, used by Sun. The initial work was, in part, to create a simple model of a processor as a teaching aid. To this end, each instruction was kept simple and executed in a single cycle, compared to the conventional Complex Instruction Set Computing (CISC), where a single instruction might carry out multiple operations requiring multiple processor cycles.
This also means, for certain application areas, higher performance, which is why, alongside the CISC families – notably those from Intel – there have, over time, been a number of RISC families; we have already mentioned MIPS, and others include PowerPC, from IBM, and Alpha, from DEC. However the biggest RISC impact has come from ARM (at one stage called Advanced RISC Machines), implementations of whose RISC architecture IP dominates the low-power end of the market.
So why is there the sudden interest in RISC-V? In part, it is because it is open source, which is fashionable in some circles, and it has an appeal to those who are not keen on buying a license and paying royalties on sales. And, I would argue, it is in part because we seem to be at an inflexion point in the industry, where there is debate about how to implement the IoT and a general feeling of uncertainty now that ARM has been bought. SoCs and ASICs at leading-edge process nodes are expensive and complex, and we are seeing comment based on the so far unproven assumption that “Moore’s Law is dead.”
RISC-V, pronounced risk five, stems from Berkeley and has been developed with the involvement of David Patterson, a key player since the 1980s in RISC projects. Unlike some previous RISC ISAs, it has been developed specifically for commercial implementation. For instance, the license: rather than the GPL (GNU General Public License), which is widely used in software but requires any user to make their implementation available to others under the GPL, RISC-V is currently licensed under the BSD (Berkeley Software Distribution) license, originally created in the late 1970s for Berkeley’s Unix derivative, which makes no demands on users to reveal their changes and implementations. Another decision was to make provision for a hypervisor and virtualisation.
RISC-V has moved out from Berkeley and is now under the umbrella of the RISC-V Foundation. This has an extremely interesting membership, including AMD, Google, Hewlett Packard Enterprise, Huawei, Microsemi, Micron, Microsoft, NVIDIA, NXP, Oracle (owners of Sun), Qualcomm, Rambus, Western Digital, and a raft of other companies. The Foundation is very active and with its members has created tools to help the transition from an ISA into real products, which we will look at in a moment.
Kevin Morris, when writing about the Microsemi announcement, discussed in broad detail the features of RISC-V, and, if you want more than that, then the Foundation’s web site is the place to go. But one important thing to remember is that while it is currently a 32-bit or 64-bit ISA, the designers have made provision for extension to 128-bit in the future – earlier RISC ISAs didn’t provide upward growth, and that has proved problematic.
Another feature that has been pointed out is that, since all aspects of an implementation using a core based on the ISA can be shown to comply with a standard development flow, it makes it much easier for the end device to be certified for safety standards.
One of the tasks of the Foundation has been to develop tools that allow the ISA to be turned into a working processor. On the website are several open-source CPU designs, together with design software, to generate Verilog for silicon layout. A processor needs software, and there are a GNU compiler tool chain, an LLVM tool chain, and other development products.
We are now seeing the first RISC-V ISA products.
SiFive, a company founded by the Berkeley RISC-V team, has launched what it calls SoC platforms – effectively, development kits for creating SoCs with RISC-V processors. There are initially two flavours. One is the Freedom U500, a Linux-capable system with performance at 1.6 GHz or higher and support for standard high-speed peripherals. It is designed in a TSMC 28nm process. The partner is the Freedom E300 Series, which has been designed for minimal area and power in a TSMC 180nm process and addresses the embedded microcontroller, IoT, and wearables markets. The Freedom platforms consist of a complete software specification, board support packages (BSPs), development boards, software tool chain, and base silicon. The first development boards use SmartFusion2 SoC FPGAs from Microsemi. SiFive is also crowd-funding an Arduino-compatible development kit, running the E310 HiFive. The seriously oversubscribed project aims to deliver the first 150 boards before Christmas.
Another crowd-funding effort is from OnChip, part of the Universidad Industrial de Santander in Colombia. They are raising money for an initial production run (around 70,000 chips) of a 160 MHz device, with a selection of open source peripherals. They are also working on a development board.
PULP (Parallel Ultra Low Power) is a project using RISC-V cores to create a high performance, high-efficiency platform. As an interim project, the team, based at the Swiss Federal Institute of Technology in Zurich, has released the PULPino, a single-core RISC-V implementation. The PULP virtual platform using multiple cores will be released sometime next year.
Codasip, a spinout from the Brno University of Technology in the Czech Republic, has created the Codix-Bk processor IP and infra-structure. They recently announced an agreement with UltraSOC to integrate the cores with UltraSOC’s IP for on-chip SoC debug, optimisation, and analytics. The two companies have also announced another partnership, with BaySand and Codeplay, for a development flow, adding BaySand’s Metal Configurable Standard Cell (MCSC – a technology for SoC/ASIC implementation) and Codeplay’s ComputeSuite software development tools for open standards middleware. This is claimed to provide a fast and economic way to develop IoT systems.
There are quite a few more announcements, many from small companies, using the ISA to create novel products and systems. There is criticism about the ISA lacking this or that, but there are two points here. The first is that we are at a very early stage in the development of RISC-V, and the second is that the philosophy of the movement is that you are free to adopt, extend, or otherwise modify the ISA to meet your own needs.
My own feeling is that we are at the beginning of an exciting way forward. I have written before about routes to creating ASICs and SoCs without massive costs. In essence, this involves using a mature production process (SiFive are using 180 nm for one of their Freedom platforms) and low-cost tools. To that you can now add an open-source route to a processor core.
There has been debate as to whether RISC-V will displace ARM and Intel. The consensus is that it probably will not, but that it will provide a third option, carrying out tasks for which the two giants do not provide the best fit, and that, over the next few years, we will see some very interesting products.