feature article
Subscribe Now

Integrity Simplified

Mentor Upgrades HyperLynx

These days, the metal on your PCB has to do a lot more than just connect a few dots. With the pervasiveness of high-speed serial interfaces and other signals that put a premium on signal integrity (SI), most board designs can’t get away with simple-minded placement and routing anymore. And, with the compression and perforation of power planes, we can’t take power integrity (PI) for granted either.

The situation is only getting worse. New protocols and standards for high-speed interfaces like DDR4, multi-gigabit Ethernet, and PCI Express put even more strain on the design, and continually increasing operating speeds combined with decreased voltages up the ante yet again. It is becoming rare for a design team to be successful with a leading-edge PCB without state-of-the art SI and PI simulation and analysis.

Unfortunately, industrial-strength power- and signal-integrity analysis tools can be intimidating and complicated to use, and they can require enormous amounts of processing power to solve the complex equations involved. Many teams have one special expert who is in charge of SI and PI for the project. Many other teams don’t even have that one expert, but really wish they did. This means the SI/PI challenge expands beyond tools – to teams and talent. 

With the newest version of HyperLynx, Mentor Graphics is working to improve all that.

HyperLynx has been around a long time, actually. The company says the tool’s biggest obstacle, ironically, is that it’s easy to use and fast, and that makes some engineers worry. After all, if it’s that fast and easy, it can’t be doing REAL work, now, can it?

We think we know what’s going on here. You know those signal integrity experts that some teams have? The ones who spend long hours gazing knowingly into the vast abyss inside their eye diagrams, mumbling softly to themselves in cryptic tongues about “pre-emphasis” or “equalization”? Those guys need to defend their turf. They need to preserve their exclusivity. After all, if SI and PI were straightforward, easy-to-use, and fast, those guys would lose all of their mystique.

But Mentor insists that no mystique is required. With the latest rev of HyperLynx, signal integrity and power integrity co-exist in one easy-to-use environment that is plenty approachable even by engineers who don’t walk around constantly chanting about crosstalk and ground bounce. The new HyperLynx release merges signal- and power-integrity analysis, 3D-electromagnetic solving, and fast rule checking into a unified environment. The result is a single GUI that manages several underlying SI/PI simulation engines to allow quick interactive analysis as well as exhaustive batch-mode analysis.

Mentor’s goal with the updated HyperLynx is to help move SI/PI analysis earlier in the design cycle to work toward first time success with new designs. Mentor says the single, easy-to-use environment contrasts with the norm of different UIs for each tool in the SI engineer’s toolbox. This unified approach makes it easier for engineers to come up to speed quickly on SI/PI – even if signal integrity is not their primary job.

The new HyperLynx incorporates two 2.5D solvers, a fast DC/IR-drop simulator, and a fast quasi-static 3D solver all in one environment. The second 2.5D solver is capable of pure power and mixed signal-and-power modeling which adds accuracy to SI simulations, useful in resolving simultaneous-switching-noise (SSN) complications. This combination of behind-the-scenes engines allows the right tool to work on the right part of the task, without bringing in multiple interfaces and manual tuning setups. 

Since SI/PI analysis is fundamentally analog (and since analog simulation tends to move in something like geologic time), brute-force simulating an entire PCB is not an option. That means we need clever strategies to apply attention specifically to the important parts. Mentor provides wizards to help tune the simulation for standard interfaces and protocols such as DDR, Gigabit Ethernet, and so forth, which can give a summary pass/fail result on an entire interface. In the case of DDR interfaces (which now includes DDR4 and LPDDR4), there is automated whole-bus simulation with consolidated results reporting. And speaking of reporting, HTML-based reports allow easy creation of design documentation and internal publication of results. 

For protocols that support Channel Operating Margin (COM), you can check the quality of links based on a complex set of simulation steps, yielding single pass/fail numbers for each channel. COM support includes the industry’s first robust commercial implementation of COM for 100Gb Ethernet with simulation details fully automated. All together, these pre-tuned interface and protocol packages simplify the setup and learning curves and optimize the simulation performance on some of the trickiest parts of a typical design.

By improving the performance of HyperLynx at the same time as they simplified the use model, Mentor has made their perception problem with HyperLynx even more challenging. If the old version was suspiciously fast and easy, then the new faster, easier version must be even worse. The company has gone to great lengths to emphasize the accuracy of HyperLynx, and they point out that making setup easier and execution faster gives all engineers – including experts – more time to spend on the parts of the design and analysis that actually matter. Power-aware SI analysis definitely puts HyperLynx in the big leagues in terms of accuracy of the modeling and simulation. 

Mentor says the new version of HyperLynx can efficiently handle very large layouts including extra-deep stackups, huge net counts, and even complete multi-board systems. The latest version includes performance enhancements for both multi-processor use and general simulation engine performance – including caching and reuse of previously extracted models. 

There are certainly other SI and PI analysis solutions in the sea, and you may well find your experts clinging to their familiar tools with a passion. With the increasing importance of this type of analysis, however, and with the scarcity of both engineering time and specialized SI/PI analysis expertise, it would pay to take a careful look at the real-world capabilities of a solution that promises to be easier and faster to use than some of the more established heavy-iron tools. 

Leave a Reply

featured blogs
Aug 17, 2018
If you read my post Who Put the Silicon in Silicon Valley? then you know my conclusion: Let's go with Shockley. He invented the transistor, came here, hired a bunch of young PhDs, and sent them out (by accident, not design) to create the companies, that created the compa...
Aug 16, 2018
All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have c...
Aug 15, 2018
VITA 57.4 FMC+ Standard As an ANSI/VITA member, Samtec supports the release of the new ANSI/VITA 57.4-2018 FPGA Mezzanine Card Plus Standard. VITA 57.4, also referred to as FMC+, expands upon the I/O capabilities defined in ANSI/VITA 57.1 FMC by adding two new connectors that...
Aug 14, 2018
I worked at HP in Ft. Collins, Colorado back in the 1970s. It was a heady experience. We were designing and building early, pre-PC desktop computers and we owned the market back then. The division I worked for eventually migrated to 32-bit workstations, chased from the deskto...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...