feature article
Subscribe Now

A Different View of FPGA

Lattice Lays an Alternative Course

For as long as most of us can remember, the FPGA game has been about bigger, faster, louder – more LUTs, more IOs, faster SerDes, more DSP – the list of things the leading vendors have piled onto tiny squares of silicon boggles the mind. The fundamental strategy has been the same: Make the FPGA the center of your system. Replace the ASIC or ASSP with an FPGA, and reap the benefits of programmability and flexibility. Of course, there has always been a “catch.” FPGAs are more expensive, more power-hungry, and slower than their task-optimized ASIC/ASSP brethren. The tradeoff space is clear. If you need programmability and flexibility more than you need that extra oomph in cost, power, and speed, choose an FPGA.

Lattice Semiconductor is charting an alternative course. Rather than expanding the FPGA to take over the entire system, Lattice has worked to design devices that bring the benefits of programmability and flexibility to your system without trying to replace your ASIC or ASSP. They want you to leave that fast, cheap, low-power ASIC or ASSP exactly where it is, thank you very much, and park one of their much more modest FPGAs alongside. The theory is, you end up with the best of both worlds – the task-optimized awesomeness of ASIC/ASSP with the flexibility of FPGA.

Recently, Lattice quietly rolled out two new members of their ECP5 low-cost FPGA family, the ECP5-5G and ECP5-12K. ECP5-5G supports up to 5 Gigabit SerDes (as the name implies) with up to 85K LUTs in a 10mmx10mm package. The largest device has 3.7 Mb of embedded memory and 156 18×18 multipliers. ECP5-5G supports multiple 5G protocols including PCI Express Gen 2.0, CPRI, and JESD204B. The much smaller ECP5-12K drops the SerDes, but offers programmable IO support for popular interface-bridging functions including LVDS, MIPI and LPDDR3. In other words, you can snuggle one of these little guys up next to your ASIC or ASSP and get a ton of flexible connectivity without having to replace your whole show with programmable logic. 

Lattice is targeting applications in the industrial, communications and consumer markets ranging from small cells, industrial video cameras, games, and broadband access equipment to LED controllers, machine vision, and motor control. Their low-cost, small form-factor, low-power strategy goes against the trends in programmable logic, but it makes a lot of sense in the system-level view of the applications they are targeting. Often we design FPGAs into a system because we need the flexibility that programmable logic provides. But, in some situations, we can isolate that need for flexibility down to a fairly small chunk of the system – usually around IOs. In a way, Lattice is leading the modern rebirth of the idea of FPGAs as “glue logic.”

It takes a fine-tuned strategy to compete in the high-stakes FPGA space against powerhouses like Xilinx and Altera/Intel. Lattice has been thoughtful and prudent in choosing where and how to engage the big guys. One of their more visible initiatives has been to take the ultra-low-cost, tiny-form-factor, negligible-power side of the FPGA spectrum. Lattice’s acquisition of SiliconBlue a few years ago gave them a unique offering in FPGAs for the mobile/consumer market that was entirely unmatched by other FPGA players. The company continues to enjoy a virtually unchallenged position in that market with their iCE family of FPGAs, but the number and diversity of customers in that space is comparatively small, and pricing pressure is extremely high (due to the incredible production volumes of devices in that market).

The bigger challenge is this low-end, high-value FPGA segment where the big players are most definitely not sitting on the sidelines. Lattice’s strategy there has been to optimize their offerings for specific types of applications. In the release for the latest announcement, the company claims a 40% cost advantage, 30% power advantage, and “twice the functional density” (meaning more LUTs in a smaller package) compared with “competing FPGAs.” While these “fuzzy, feel-good” comparative numbers are always a good cause for skepticism, Lattice does back up their claims with a decent amount of data. They show, for example, that you can have a fully functional SerDes design consuming as little as a quarter-watt of power. That’s pretty miserly when it comes to power budgets for SerDes, regardless of what you might consider “competing FPGAs.” 

Lattice is rebelling against FPGA industry norms in other ways, too. In a market where the standard procedure is to announce products years before they are available, Lattice typically doesn’t start talking about a new offering until the product is ready to ship and is supported in the tool suite. That’s a refreshing change, particularly if you’re like most engineers – when you hear about a new solution, you want to get started with it right away. Nothing is more of a let-down than learning about an awesome new capability that will solve all your engineering woes, only find out that you won’t be able to touch it for 24 months or more.

While Lattice is comparatively quiet, some of their solutions are very compelling. If your design is in one of the sweet spots they’re targeting, it might pay to check out what they offer. You might find some good benefits walking the alternative path. If you’ve dealt with Lattice in the distant past, you might find some refreshing changes. Gone is the stodgy, old-school culture, replaced by a more collaborative and energetic culture that must manifest itself all the way into customer engagements. Sometimes, that aspect of a company is just as important as the differentiation in the products themselves.

14 thoughts on “A Different View of FPGA”

  1. Pingback: listen to music
  2. Pingback: Dungeon
  3. Pingback: DMPK Services
  4. Pingback: friv
  5. Pingback: website for game
  6. Pingback: Aws Alkhazraji
  7. Pingback: see this site
  8. Pingback: go right here
  9. Pingback: coehuman Diyala

Leave a Reply

featured blogs
Nov 24, 2021
The need for automatic mesh generation has never been clearer. The CFD Vision 2030 Study called most applied CFD 'onerous' and cited meshing's inability to generate complex meshes on the first... [[ Click on the title to access the full blog on the Cadence Community site. ]]...
Nov 24, 2021
I just saw an amazing video showing Mick Jagger and the Rolling Stones from 2021 mixed with Spot robot dogs from Boston Dynamics....
Nov 23, 2021
We explain clock domain crossing & common challenges faced during the ASIC design flow as chip designers scale up CDC verification for multi-billion-gate ASICs. The post Integration Challenges for Multi-Billion-Gate ASICs: Part 1 – Clock Domain Crossing appeared f...
Nov 8, 2021
Intel® FPGA Technology Day (IFTD) is a free four-day event that will be hosted virtually across the globe in North America, China, Japan, EMEA, and Asia Pacific from December 6-9, 2021. The theme of IFTD 2021 is 'Accelerating a Smart and Connected World.' This virtual event ...

featured video

Integrity 3D-IC: Industry’s First Fully Integrated 3D-IC Platform

Sponsored by Cadence Design Systems

3D stacking of ICs is emerging as a preferred solution for chip designers facing a slowdown in Moore’s Law and the rising costs of advanced nodes. However, chip stacking creates new complexities, with extra considerations required for the mechanical, electrical, and thermal aspects of the whole stacked system. Watch this video for an overview of Cadence® Integrity™ 3D-IC, a comprehensive platform for 3D planning, implementation, and system analysis, enabling system-driven PPA for multi-chiplet designs.

Click here for more information

featured paper

Utilizing the Benefits of Coupled Inductors

Sponsored by Maxim Integrated (now part of Analog Devices)

In a multiphase design, coupled inductors offer many advantages compared to discrete inductors including current ripple cancellation, improved transient performance, higher inductor current saturation, smaller inductor size, output capacitance and improved overall efficiency performance. This application note highlights how the benefit of current ripple cancellation can be traded for either smaller size or higher efficiency, depending on design specifications.

Click to read more

featured chalk talk

Seamless Ethernet to the Edge with 10BASE-T1L Technology

Sponsored by Mouser Electronics and Analog Devices

In order to keep up with the breakneck speed of today’s innovation in Industry 4.0, we need an efficient way to connect a wide variety of edge nodes to the cloud without breaks in our communication networks, and with shorter latency, lower power, and longer reach. In this episode of Chalk Talk, Amelia Dalton chats with Fiona Treacy from Analog Devices about the benefits of seamless ethernet and how seamless ethernet’s twisted single pair design, long reach and power and data over one cable can solve your industrial connectivity woes.

Click here for more information about Analog Devices Inc. ADIN1100 10BASE-T1L Ethernet PHY