For more than two decades, the promise of high-level design methodologies has been dangled in front of digital hardware designers. High-level design was going to revolutionize our design process. It would make us dramatically more productive. It would make us vastly more agile and adaptable as our design requirements evolved. It would make us into Super Engineers – or it would take away our jobs.
Everyone who has designed at the register-transfer level (RTL) using hardware description languages (HDLs) such as VHDL and Verilog knows, deep down in their bones, that RTL is not the answer. The detailed, nit-picky, verbose, cryptic, architecture-specific, technology-locked nature of RTL design is almost incomprehensibly clunky. Yet, for more than twenty years, it has persisted as “the way it’s done” when designing digital hardware.
High-level design tools such as high-level synthesis (HLS) take a much more abstract approach. By describing the behavior we want (rather than the specific hardware architecture we have designed to implement that behavior), we can capture our design intent with a tiny fraction of the number of lines of “code.” Fewer lines translates into faster design creation, fewer bugs, easier modification, faster iteration, and more fulfilling lives for hardware developers. Yet, for more than twenty years, the technology and methodology has been out of the reach of most mainstream designers.
In part, the technology has been out of reach by design. EDA companies put astronomical price tags on their high-level design tools – partly because of the extreme benefits (often more than 10x productivity, translating into much shorter design cycles) and partly because the new methodology required a considerable amount of support. EDA companies joked internally that they needed to ship an applications engineer (AE) with every copy of the software, just to keep the customer on track.
Now, Xilinx is putting an end to all that.
With their newly announced HLx initiative, Xilinx has released an integrated tool suite that brings high-level design to the masses. The company already claims more users of high-level synthesis than the rest of the industry combined, but now Xilinx is going the rest of the distance to make high-level design the default approach for many applications. With the new Vivado Design Suite HLx editions, every edition includes Xilinx’s HLS technology. But, beyond HLS, the company has put together a comprehensive flow and ecosystem that should allow the average designer to take advantage of the enormous productivity, quality, and flexibility gains that high-level design can deliver.
The net result? Xilinx claims a 10-15x productivity improvement over conventional design methodologies on the first implementation, and as much as 40x on subsequent reworks of a design. Those are obviously some pretty staggering numbers. After all, who wouldn’t want to shrink a 1-year project into a single month?
Surprisingly, engineers over the years have been a little reluctant to dive into the HLS pool. For some, their prowess in RTL design is a source of pride, not unlike what many of us in software felt about our assembly language skills when higher-level programming languages began to pick up steam. Similarly, many engineers argue that they will always be able to do a “better” job than an automatic tool at detailed hardware design. But the handwriting is on the wall. Those who stick with a purely RTL design approach are doomed to fall behind. When you’re the last lumberjack swinging an axe while the rest are using chainsaws, your competitive days are numbered.
The Xilinx HLx solutions go far beyond simply including high-level tools in the suite. Xilinx is combining tools, IP, reference designs, methodologies, and boards that work together to get you from zero to a working design in the shortest possible time. The platform itself does most of the heavy lifting – particularly on the non-differentiating parts of your design. Nobody is going to be successful because the USB interface to their system is somehow magically “more standard” than their competitors’ products. You are going to succeed because all of the mundane parts of the system “just work” and you have the ability to focus your energies on the critical bits where you can really make a difference – your secret sauce, the value-add.
The new “HL” editions of Xilinx Vivado tools suite are HL System Edition, HL Design Edition and HL WebPACK™ Edition. Nope, that was not a typo. Even the webpack edition includes high-level design capabilities such as C-based high-level synthesis and IP Integrator. It’s a whole new world out there for the mainstream designer.
Many companies will use HLx to build a platform on top of a platform. They will combine standard IP blocks, high-level architectures, reference designs, and even tool flows to create company-specific platforms that will let their various design teams start off even closer to the finish line. This kind of knock-on productivity boost could be a compelling advantage for organizations that take advantage of it intelligently.
One key aspect of Xilinx’s high-level methodology is getting quick closure on the connectivity aspects of your design. The company’s IP integrator understands the features of the boards you are using and directs you quickly to pre-designed connectivity standards, eliminating the risk of descent into standards hell that can result from trying to cook your own implementation of today’s complex interfaces.
Also, because the primary design description is in higher-level languages than RTL, simulation is exponentially faster than with RTL-based design. Faster simulation translates into faster iteration, both in terms of how fast it is to isolate and make desired changes and how fast the environment can propagate those changes through to the final implementation. The whole rest of Vivado has already been optimized to improve iteration and turnaround time, and those improvements work hand-in-hand with the high-level methodology to deliver the productivity and ultimately schedule improvements.
The high-level methodology also very effectively isolates the design from the implementation specifics. So, if you later need to retarget the design to a different technology, modify the architecture to meet evolving requirements, or re-use parts of the design as components in other designs, the high-level specifications give you substantially better flexibility than their RTL counterparts.
Along those lines, HLx facilitates re-use at a whole new level. Taking a component into a new context is much easier when the implementation architecture isn’t hard-coded into the original version. IP developed with higher-level languages can easily be adapted, modified, and re-purposed without the massive overhead of designing a new architecture and re-writing RTL code.
Backing away to a system-level view, Xilinx HLx is the hardware engineer’s answer to the company’s previously announced SDx series. Where SDx (software-defined whatever) boosts the productivity of the software development team, HLx helps out the hardware designers working in the next office over. It makes sense. In both the hardware and software world, the majority of every design these days is “platform” – standard components and interfaces that are required to achieve basic functionality but do not contribute to product differentiation.
The ideal world for any team is to spend their time and energy on the things that will make their product shine, and that’s what Vivado HLx is ultimately about.
15 thoughts on “High-Level Design for Everyone”
The good news from history’s perspective, is that you really don’t need to learn HLx if you plan to retire in the next few years. You are likely to be employed maintaining the existing RTL designs up until those services are no longer needed, or some kid replaces the RTL design with a better HLx design.
It took about a decade for C to replace assembly programming for operating systems work. And less than that for Basic/COBOL/Fortran/Forth/Pascal/ADA to replace assembly applications coders.
A special thanks goes to the teams that pioneered HLS during the last two decades, for not giving up the faith when the RTL guys sneered it was impossible.
University of Toronto’s TMCC is one of the first FPGA C compilers, with work starting in 1994 and presented at IEEE’s FCCM95. This predated the evolution from the Handel language to Handel-C work done shortly afterward at Oxford University Computing Laboratory (later available commercially by Celoxica). Streams-C from Los Alamos National Laboratory (later available commercially as Impulse C)
And the hard work of a lot of applications engineers that suffered the arrows in the back problems, as the technologies grew and matured.
As the “Father” of HLx at Xilinx it’s good to see it become mainstream. I wrote a blog on this Monday giving a little of the history. It got me thinking about Gary Smith and the 20 year journey to get here…
Best to your readers,
Uh yeah. This is epically awesome. Here’s a table with the full HL Vivado feature/version breakdown for those interested: http://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html
You’ll notice they essentially did away with the Vivado WebPACK voucher requirement for the Logic Analyzer as well, which is also pretty awesome.
Guess it’s a good thing that you can pick up a wireless Zynq dev board for $55 now (insert shameless plug): http://snickerdoodle.io
Next stop: SDSoC???
“c-to-vhld” or “HLx” won’t produce as hardware-efficient an implementation as hand-coded VHDL but nobody will care if the time-to market is 10x quicker.
Also, managers will hire ‘c’ coders who are 2-a-penny and know nothing about hardware, to do the coding (and the result will be terrible designs), because managers won’t “get” that you still need guys who understand the hardware to write the correct lines of ‘c’. Of course by the time they realise this, the expensive VHDL guys will all have been fired.
I am an VHDL designer and I would just like to relay an actual conversation I had with the system designer recently.
Me: Hi, what are you working on.
Him: Oh, I just designed this new component to do (redacted information).
Me: That’s great, have you written a ‘C’ model to prototype it?
Him: Sure, I have done that and tested it.
Me: Great, when do I start implementing it in VHDL. It sounds fun.
Him: You don’t. I used c-to-vhld, it is finished.
Me: Erm, so what do I do?
So yes, basically there goes another career down the toilet. My hard-won VHDL skills are going to be pointless, along with my 6502 assembler skills, my amazing ability with DOS batch files, and my ability to do technical drawings (which were invalidated by the invention of CAD software)
All this means is that I am going to have to learn something else (yet again) to stay employable.
Sigh, I am getting too old for this sugar*.
(*saved by auto-correct once again)
@NicholasLee – C/C++/SystemC, VHDL and Verilog are just tools. The experience that you gained in VHDL design can be applied to C-based design, that was a reason for developing the SystemC library and TLM-2.0 interface standard (warts and all).
With your system architect, you can advise on the hardware design to optimize the C-to-RTL high level synthesis (HLS). Likewise, your software engineering colleagues can help to optimize the system code that runs on a processor(s).
In ESL (forgive me for using that term, I know that it has fallen out of favor), HLS has become the base of a bottom-up methodology development. Kudos to Xilinx for taking advantage of that.
But as designs become more complex, engineers will need design creation technologies to develop those. There are a number of design creation environments ready to step up including my firm’s.
In the bigger picture, to learn about system level design, please take advantage of our Resources page at Space Codesign, view our presentations on SlideShare and YouTube. Be welcome! (or as we say in Montreal: soyez les bienvenus!)
P.S.: Twenty years ago, people were arguing against HDL’s for not creating designs as optimal as schematic capture. Now, there are still cases for custom design and in the future, RTL will still be around for high performance design after C-based design takes over in the mainstream (as RTL once did).
Highlevel Language Design Methodologies sounds great to me.
One question: Why only C and C++ as the highlevel languages?
Wouldn’t there be interest in using languages like Java, Python, Scala, Clojure etc. for direct FPGA synthesis. If a couple highlevel languages is good, would say the choice of 10 more highlevel languages be better?