Consolidation, consolidation, consolidation. If you’ve been following the news in the semiconductor market this past year, you’ve seen acquisition after acquisition. There is no doubt that there is a big consolidation underway in the semi space. And consolidation is nothing new. We have watched little semiconductor companies join to become bigger and bigger semiconductor companies for years.
But this time, it’s different.
The last big consolidation was manufacturing driven. Chasing Moore’s Law at the fab level got so expensive that only the largest, best-funded organizations could tackle it. That led us down a path of consolidation to the comparatively small number of companies actually manufacturing semiconductors today. It also led to the genesis of the fabless semiconductor revolution. If you couldn’t afford to build a fab, you could still start a chip company and outsource the manufacturing part to others.
Now, even the fabless side is consolidating. Again, the barrier to entry became excessively high – with hundred-million dollar tabs not unusual for bringing a new device to market. At the same time, venture funding all but dried up for semi startups, with the big bucks being pulled away by the Facebook effect. The potential upside in software and social media was so high, and the required investment so low, that antsy money fled the semi space for faster, potentially greener pastures.
In some semi segments, the entrenched fabless companies built up substantial barriers to entry for newcomers. In the FPGA market, for example, numerous attempts to breach the Xilinx/Altera walls have failed, leaving behind a sad trail of broken dreams. The failures have largely vanished into large puffs of negative ROI. The hearty players that remain have been the subject of consolidation – often mirroring the integration on devices themselves. When widgets and franistans first get integrated on one chip, independent widget and franistan companies combine to make widgistan companies. As integration continues, so does consolidation.
Now Moore’s Law has reached its economic, if not its technological end. Yes, we can make chips at 10nm, 7nm and beyond. But there will be few applications that are able to make economic sense out of manufacturing at those process nodes. Again, looking at the FPGA industry, only the most exotic devices are currently being fabricated on the leading-edge nodes. Mainstream FPGAs make more sense at stable, legacy geometries where yields are high, NREs are lower, and processes are stable.
This slowing of the next-node express gives innovation a chance to breathe.
In the past, there was little reason for chipmakers to focus on anything beyond getting onto the next node as quickly as possible. By jumping onto a new node, everything about your product was better automatically. Costs went down, performance went up, power efficiency went up, and new levels of integration became possible. This double-everything bonanza left little room for lower levels of optimization. You didn’t want to be fiddling around with some meager 20-30% improvement and miss the boat when your competitors jumped to the next node and got all their goodies doubled.
Now, with far less motivation to move to the next process, there is time and incentive to innovate in other areas. We have the luxury to tune tools rather than constantly focusing on increasing their capacity. We can build IP blocks that have a longer useful life before having to be re-engineered for a new process geometry. We can, and we must find new ways to innovate, rather than lazily letting Moore’s Law do our heavy lifting for us. Hardware platforms will become more stable and standardized, tools will become more robust and capable, and IP, reference designs, and development kits will dispose of more and more of the engineering drudgery, leaving us to focus our energies on adding real value and differentiation to our creations.
Real innovation will move to the leaf nodes of engineering, away from the infrastructure. Fewer, larger semiconductor and tool companies will provide more stable platforms, but with a much lower innovation rate than we see today. Systems-in-package will combine disparate technologies into small, efficient form-factors. Processing power will be almost free – both from a unit cost and from a power perspective. System-level designers will have an unprecedented base from which to create new technology.
For us as engineers, this means that it is time to change as well. It is easy to become complacent, relying on accumulated expertise in esoteric technology areas. As innovation moves to the leaves, traditional engineering disciplines will be commoditized. Today’s cutting-edge ideas will be designed into tomorrow’s off-the-shelf IP and made available to the world as building blocks. Engineers who put their value in specific knowledge will fall by the wayside, and those whose talent is learning and adapting will succeed.
The time has also come to tear down the wall between software and hardware. It will be a rare project that relies on only one of these disciplines. It will also be a rare project that does not require close coupling between the two. The dividing line between hardware and software will fade into relative obscurity, and the engineer who is adept at both sides will be well prepared for the next era in design. (Wow! This paragraph sounds like a collection of engineering fortune cookies.)
Hopefully, the rug will not be pulled out from under semiconductor innovation too soon. Initiatives such as Silicon Catalyst are working to pump new blood into the semiconductor startup arena. With the demands of the exploding IoT upon us, we’ll need the right semiconductors, sensors, power, and packaging technologies to achieve the real potential of IoT. If that hurdle is cleared, we should see a large crop of small, innovative startups surfing on top of a giant wave of technology from the back side of Moore’s Law.
With all this, the next ten years will not be like the previous fifty. The impact of the front side of Moore’s Law will crawl to a stop while the innovation boost from the back side pulls innovation in end products forward at a possibly unprecedented rate. Buckle your seatbelts, engineers. It’s gonna be an exciting ride.