feature article
Subscribe Now

Emulating the Success of Others

Soft Machines Reveals Shasta, its First VISC Processor

“Imitation is the sincerest form of flattery” — Charles Caleb Colton

If you’ve been keeping up on weird, ambitious microprocessor designs – and really, who doesn’t? – you’ll no doubt remember Soft Machines and its VISC architecture. We first talked about VISC back in November and December of last year, so it’s been almost 12 whole months without an update. That’s like waiting for new Game of Thrones material.

Well, wait no more. Soft Machines has… uh… teased us some more. There’s no actual chip yet, but that’s coming Real Soon Now. About mid-2016, according to the company’s in-house prognosticators. And with a CPU design this ambitious, that means it’s got to be very close to finished.

Let’s review: VISC (which is just a name; it doesn’t stand for anything) is a high-performance 64-bit processor that can run software written for other microprocessors. It can be ARM-compatible; it can be x86-compatible; it could conceivably run SPARC, PowerPC, MIPS, or 8051 assembler code. It’s a chameleon. Or maybe a more apt simile is a fork-tailed drongo. VISC mimics its fellow creatures and steals their food. 

But in a good way. And certainly in a very clever way. The VISC microarchitecture is extraordinarily complex, comprising multiple CPU cores combined with multiple virtual cores that aren’t really CPU cores, but that software thinks are CPU cores. Confused yet? Then there’s the software-translation layer that allows VISC to execute unmodified ARM binaries (for example) faster than an actual ARM chip can. Then there are the power-saving measures, which make VISC more power-efficient than other processors as well, according to the company. So you get a CPU that’s faster, more efficient, and more flexible than any CPU you’ve ever seen. Sold yet?

Hang onto your cash, because we haven’t gotten to Shasta. Shasta is Soft Machines’ first real, commercial implementation of the VISC architecture. Sure, the company has made prototype silicon before, but those chips weren’t for sale. Shasta will be the first VISC we can get our hands on, sometime around the middle of next year.

In addition, the company has announced Mojave, the customizable, customer-defined, integrated version. Don’t like the (comparatively) generic Shasta design? Soft Machine will happily make you a custom Mojave with two Shasta processor complexes, a ton of graphics and peripheral I/O, and whatever additional features you need. Mojave chips aren’t really intended for the mass market. They’re a semi-custom way for OEMs to get their own VISC processor without designing one from scratch.

Shasta is being fabbed in TSMC’s 16nm process, an aggressive start for a new company. The chip is expected to hit 2 GHz or thereabouts, and it will have two physical CPU cores and support for two virtual CPU cores. Remember that VISC doesn’t require a 1:1 mapping of virtual cores to physical cores. There can be more of one than the other. For example, a single software thread might require the resources of both physical cores for certain complex tasks. On the other hand, two lightweight threads could map onto just one physical CPU core. The virtual-to-physical mapping changes all the time, even cycle-by-cycle, depending on what the host software is trying to do.

The good news is, you never need to learn how to do this yourself. The thread formation, scheduling, and mapping are all done in hardware. In fact, those tasks collectively account for nine or ten stages (it depends) of VISC’s 18-stage pipeline.

That’s not counting the software-translation layer that is VISC’s primary party trick. Shasta gobbles up incoming binary code like any processor, but then it converts those opcodes into its own internal instruction set. To be fair, many high-end CPUs also do binary translation on the fly. Think x86 and its obscenely complicated ISA. Intel and AMD have been converting those x86 instructions into RISC-ified internal instructions for years, and it seems to work. In that sense, VISC isn’t doing anything the others haven’t done before.

The difference is that VISC is emulating (or “hosting,” in the company’s vernacular) other processors’ instruction sets. Soft Machines says that Shasta will support two “guest” instruction sets in addition to its own native ISA, but they won’t say which ones.

One of the two is obvious. The company has been upfront about its intention to offer ARM compatibility – with its publicly shown demos – but it’s a lot more coy about the other “guest” software it will support.

Shasta is being pitched as offering “server-class performance at mobile power” levels, and servers seem like the company’s first target market. When thinking of servers, most minds instinctively snap to x86, given Intel’s dominance of that space. And indeed, VISC might offer x86 compatibility – someday. But today is not that day.

I think Shasta will offer compatibility with ARM and MIPS, but not x86. If Soft Machines wants to break into the server market, there are a lot of MIPS servers feeling a bit orphaned right about now. Back in the day, MIPS Computer Systems and Silicon Graphics were on a path to make MIPS the premium high-end RISC processor for engineering workstations. But those days are long gone, and Imagination Technologies (MIPS’s current caretaker) is more interested in embedded SoC designs than in big iron. If you’ve got any MIPS-based servers lying around, you’re in need of a roadmap, and pronto. Enter Soft Machines and its VISC-based path out of the woods. It doesn’t hurt that Soft Machines is already working with Imagination on the latter’s PowerVR GPU technology. So there’s history.

SPARC would be another logical choice, and for similar reasons. Or PowerPC, another one-time high-flyer that’s gone approximately nowhere in the last decade. All three CPU families made their mark in servers but are now relegated to embedded or proprietary systems. They’re ripe targets for Soft Machines and its changeable CPU strategy.

Interestingly, Soft Machines has suggested that Shasta could support two guest ISAs at the same time, but it won’t. That is to say, the company will initially configure – I hesitate to say cripple – the chips to support only one guest ISA or the other, but not both. Even though juggling two ISAs is doable, it’s not commercially attractive. Why give away one CPU emulator when you can charge double for two? So at least at the outset, you’ll need to order your Shasta chips with either Brand A compatibility or Brand B compatibility. Don’t be surprised if they’re different prices.

Why no x86 compatibility? Given the company’s focus on servers, wouldn’t that be the obvious choice? Yes, and it wouldn’t be the first time that a company’s business plan started with some variation of the phrase, “If we can just take 5% market share away from Intel…” Precisely none of those companies exist today.

There’s your first reason. Competing with a semiconductor superpower means you’re likely to get nuked before you can load your flintlock. Second, emulating the x86 instruction set is legendarily difficult and fraught with disaster. And lawyers. And pain. Soft Machines is careful to avoid comparisons with Transmeta, the last company that tried (and failed, expensively) to outdo Intel and AMD in the x86 market. That path leads to madness and bankruptcy.

Finally, Intel is doing a pretty good job on its own, if you haven’t noticed. Its server processor lineup is full and healthy and robust and has a bright future. The roadmap looks good, and there’s little reason to think that thousands of happy server designers are in any hurry to abandon Intel and switch to another CPU supplier. Especially if that supplier is a new startup peddling its very first chip. “Thanks anyway; come back in ten years when you’ve got 1000 customers under your belt.”

That leaves the stranded MIPS, PowerPC, or SPARC users who have few alternatives for upgrading their hardware. Plus the existing ARM users who want to break into servers on the back of VISC silicon. If Soft Machines’ benchmarks can be believed, VISC can outperform any ARM processor out there and do so using less energy. In that sense, VISC is the upgrade from ARM processors. Maybe the upgrade from a lot of processors. Do you believe in virtual reality? 

Leave a Reply

featured blogs
Jun 6, 2023
Learn about our PVT Monitor IP, a key component of our SLM chip monitoring solutions, which successfully taped out on TSMC's N5 and N3E processes. The post Synopsys Tapes Out SLM PVT Monitor IP on TSMC N5 and N3E Processes appeared first on New Horizons for Chip Design....
Jun 6, 2023
At this year's DesignCon, Meta held a session on '˜PowerTree-Based PDN Analysis, Correlation, and Signoff for MR/AR Systems.' Presented by Kundan Chand and Grace Yu from Meta, they talked about power integrity (PI) analysis using Sigrity Aurora and Power Integrity tools such...
Jun 2, 2023
I just heard something that really gave me pause for thought -- the fact that everyone experiences two forms of death (given a choice, I'd rather not experience even one)....

featured video

The Role of Artificial Intelligence and Machine Learning in Electronic Design

Sponsored by Cadence Design Systems

In this video, we talk to Paul Cunningham, Senior VP and GM at Cadence, about the transformative role of artificial intelligence and machine learning (AI/ML) in electronic designs. We discuss the transformative period we are experiencing with AI and ML and how Cadence is revolutionizing how we design and verify chips through “computationalizing intuition” and building intuitive systems that learn and adapt to the world around them. With human lives at stake, reliability, and safety are paramount.

Learn More

featured paper

EC Solver Tech Brief

Sponsored by Cadence Design Systems

The Cadence® Celsius™ EC Solver supports electronics system designers in managing the most challenging thermal/electronic cooling problems quickly and accurately. By utilizing a powerful computational engine and meshing technology, designers can model and analyze the fluid flow and heat transfer of even the most complex electronic system and ensure the electronic cooling system is reliable.

Click to read more

featured chalk talk

High Voltage Stackable Dual Phase Constant On Time Controllers - Microchip and Mouser
Sponsored by Mouser Electronics and Microchip
In this episode of Chalk Talk, Chris Romano from Microchip and Amelia Dalton discuss the what, where, and how of Microchip’s high voltage stackable dual phase constant on time controllers. They investigate the stacking capabilities of the MIC2132 controller, how these controllers compare with other solutions on the market, and how you can take advantage of these solutions in your next design.
May 22, 2023