Let’s get one thing clear right off the bat. eASIC does not make FPGAs. As their name implies, they make ASICs (sort of). But their ASICs might just be the best solution for your next FPGA design. They’ll do what you were probably wanting your FPGA to do, only faster, with less power, and at lower unit cost.
The catch is, they are not “field programmable” or reprogrammable. Just like regular old ASICs, they come from the factory all configured with your custom design. Unlike ASICs, however, they don’t cost an arm and a leg in NRE and mask charges, they don’t take months-to-years and a small army of engineers to produce, and they can be customized in extremely small quantities. So, if your FPGA is really an “ASIC replacement,” you might want to see what eASIC can do for you.
The company has been around for several years now. They’ve been fairly quiet until recently, as they’ve been primarily engaged with a small number of larger customers and not marketing to the masses. Their older 90nm “Nextreme” technology resembled an FPGA in many ways. In those days, the logic was look-up-table (LUT)-based. But, rather than making configuration connections and LUT customization with SRAM-like memory cells (as FPGAs do), eASIC made those connections by direct-write e-beam technology.
In the newest generations, the company has done away with the e-beam step. Now, they customize with a single via layer using a combination of via logic, full adders, and D flip-flops. This reduces area and improves performance compared with their previous architecture, plus they have made significant gains from advancing to smaller process nodes. The result is a device that is comparable in capacity and feature set to the largest FPGAs, but with significantly better performance (the company claims up to 2x) and dramatically reduced power consumption.
The single via layer for customization is what saves the big bucks and eliminates the big risks when compared with a typical many-layer ASIC customization process. Expensive steps like layout verification have already been done on the base array (similar to an old-school gate array in that respect), so the only thing that needs to be created and verified is the single via layer.
OK, but what if you’re not doing a typical “ASIC replacement” FPGA application? One of the biggest emerging markets for FPGAs is compute acceleration. While reprogrammability would seem on the surface to be a requirement, eASIC has actually made significant inroads in this area as well. This week, the company announced collaboration with ASOCS, a company developing virtual base stations, to have their devices act as compute accelerators for off-the-shelf servers in virtual base station applications.
As long as the acceleration needs are constant across a decent number of units and reconfiguration is not a requirement, eASIC’s devices can be faster and more power efficient as compute accelerators than FPGAs. But, because of the lower NRE and faster turnaround, the cost and risk are substantially lower than a conventional ASIC solution.
It turns out that many compute acceleration sockets do not require reprogrammability. If your systems are not general purpose, it is often possible to nail down the acceleration part and lose the requirement for in-system programmability. That’s why eASIC and Intel announced earlier this year that they would be collaborating on datacenter acceleration.
eASIC’s current flagship platform, Nextreme-3, is built on TSMC’s 28nm HP process (similar to most current production FPGAs). The company claims up to 80% lower power consumption than FPGAs, and up to twice the performance of 28nm FPGAs. Because the devices do not require configuration, there is no start-up bitstream process and no configuration hardware required (which saves some more on your BOM, compared with an FPGA solution). The devices contain up to up to 18M equivalent ASIC gates of logic (actually up to 1.8M “eCells,” where an eCell is roughly equivalent to an FPGA LUT), 56Mb of embedded block RAM, and 12.5 Gbps SerDes I/O. There is also a power saving feature called “GreenPowerVia” that disables the power from unused logic. For non-volatile storage of data such as keys, there is “eFUSE” storage. Packages range from 316 user pins with 8 multi-gigabit IO to 770 user pins with 52 multi-gigabit IO.
The overall design flow resembles that of FPGAs, with an HDL flow that includes synthesis, simulation, place and route, and design analysis, debug, and verification. If you’re an FPGA designer used to doing your debug in your development board, you might need to tweak your design process and expectations a bit, but things should otherwise seem pretty familiar. From the time you supply your design with final timing constraints, the company can get you packaged prototypes in as little as 7 weeks (which is much faster than typical full-blown ASIC turnaround time).
The company says NRE typically comes in at less than $400K, including design services to convert your design and the manufacturing of prototype units. Again, this is far lower (probably by a couple of digits) than what you’d expect for a full-blown ASIC using the same process technology.
eASIC has found a sweet spot in between ASICs and FPGAs. For low- to medium-volume applications that do not require in-system programmability, there are compelling benefits to their solution in terms of unit cost, performance, and power consumption. For many users of FPGAs, that warrants consideration. Because the NRE isn’t zero, and because there is a several-week turnaround time, your design process will have to be a little tighter than many FPGA shops run, and your risk tolerance a little greater. But, if you’ve got your design already stabilized and working in an FPGA, you’ve already mitigated most of that risk. Converting your FPGA design into an eASIC implementation should be a pretty straightforward process, so you could still plan an FPGA implementation when your system is on wobbly legs and mature into an eASIC version once it’s solid.
9 thoughts on “(Almost) Like FPGAs, Only Better”
Oh YES 🙂
Now for a device that is the best of both … large dense hard logic IP section for core invariant algorithms, plus a fair sized FPGA section, for the data center compute applications.