The PCB Design tool race is perhaps the most stable and long-lived competition in all of electronic design automation. Since at least the 1980s, commercial tools have fought to own the screen of board designers as they convert ideas to schematics to metal traces etched into a substrate. Through all of those decades, the basic process has always been the same. Craft a schematic drawing with components from a library, verify that the thing will probably do what you intended, and create a board layout that physically hooks the parts up the way you specified.
Board design tools have never seen the kinds of explosive market growth – or the dramatic revolutions in methodology – that other areas of EDA have experienced. Where chip design went through waves of revolutionary change from schematic to language-based design to high-level specification, the level of design abstraction in PCB design has remained remarkably stable. While automation has become de-rigueur in the IC layout world, mandated by the sheer exponential growth in the volume of objects presented by Moore’s Law, PCB designers have floated quietly atop the integration level of physical components, seeing little more than a linear increase in the number of pins on a package over the years – their layout process remaining remarkably manual.
As a result – at first glance, the PCB design tools from twenty years ago wouldn’t seem all that different from those in use today.
Behind the scenes, however, the tectonic plates of the PCB world have quietly shifted. New stresses have built up that conspire to shake the foundation of modern board design. Boards have gotten smaller, pin counts higher, geometries tighter, power planes more perforated, frequencies higher, signal integrity more critical – pummeling the system designer from all sides. And, the EDA companies that produce PCB tools have been working frantically to create solutions that can address those pressures.
Cadence Design Systems, like many of the major PCB players, has two major tiers of PCB design tools – a “desktop” suite for solo or small-team designers, and an “enterprise” suite for large, complex, often geographically dispersed design teams. Also, like most of the major board EDA companies, Cadence got their desktop solution via acquisition. Cadence acquired OrCAD way back in 1999, and their desktop tools carry that banner still today.
What they do not carry, however, (much to Cadence’s credit) is the burden of multiple legacy source code bases. When Cadence re-vamped both OrCAD and their enterprise-class Allegro suite, they built them on a common code base. This allows the company to attack both markets with one development team, takes advantage of enhancements and bug fixes across both customer bases, and allows the company to be very agile when it comes to deciding which features to enable for which product family. Smart move, Cadence.
With the most recent release of both tool suites, we can see evidence that this foresight is paying dividends. The company decided to apply major improvements for rigid-flex design across both offerings, for example, doubling down on their development of an increasingly important feature.
The 17.2-2016 release of Allegro includes a number of improvements intended to both speed up and reduce risk from the board design cycle. Purpose-built rigid-flex support should significantly reduce the time compared with the more manual and somewhat kludgy approach that many teams have used to coax rigid-flex design out of the previous incarnations of Allegro. The system now allows stacking of substrate layers by zone, so “flex” zones can be defined with different stackups than “rigid” zones. Extensive in-design inter-layer design rule checks make sure that you don’t put a non-flexy thing in a flexy place, or otherwise commit infractions that could eventually bounce your design back from fabrication. The new DRC supports 12 new layers and 19 new surface finishes, and it can be extended by the user to accommodate new technology requirements.
Material inlays can be specified for mixed technology boards, saving considerably on materials cost, if, for example, your board has a small section that requires high-speed materials while the rest could use standard materials. New arc-aware routers are also particularly useful for rigid-flex designers, pushing-and-shoving your design more quickly to completion.
Speaking of getting your design to completion, Cadence has introduced a new approach to concurrent team design with this release. In addition to the conventional approach of pizza-slicing the design into chunks and assigning each chunk to a different designer, Allegro now supports synchronous concurrent design with multiple team members working on the same area at the same time. Because different teams work differently, you can use either an ad-hoc setup where the first person to start “owns” the design and others can join in by connecting to the host’s machine, or a structured setup where the design is initialized on a server and team members can join and leave as they please. Cadence says that up to five designers can work concurrently on a design via a LAN, cutting routing time by as much as 80%.
With signal integrity becoming increasingly more important, integration between layout tools and integrity tools has also become critical. With the new release, Allegro has made big strides in integration with Cadence’s popular Sigrity signal and power integrity solution, with tabbed routing, custom return-path via structures, extended in-design DRC rules for back-drilled vias, and power integrity for PCB designers. Tabbed routing automatically inserts trapezoidal regions along traces – helping with impedance control and crosstalk management, and enabling longer break-out lengths on external layers. The custom return via path structures allow you to define pre-verified strategies for return vias, eliminating issues that might crop up farther down the line. The new backdrill rules include finished hole size, backdrill size, start layer, must-not-cut layer, and backdrill clearance anti-pad size. Now, you can backdrill with renewed confidence.
The new power-integrity features for PCB designers takes a lot of the routing PI work off the table, leaving only the most challenging problems for your team’s PI experts. The new features take advantage of both Allegro and Sigrity technologies, providing faster access to IR-drop analysis results, allowing board designers to more effectively meet power distribution network requirements.
A host of other structural improvements round out the new release’s offering, including 64-bit support, an expanded cross-section editor, and a new padstack editor. Overall, the company claims that the new release will deliver substantial improvements in design team productivity and time-to-market.
Moving down the family tree to the OrCAD tools, the “PCB Designer” component inherits the rigid-flex enhancements already described for Allegro. PSpice technology aimed at the IoT crowd provides a framework for full-system simulation at multiple levels of abstraction – including hardware-in-the-loop approaches, where actual hardware can be used in a simulation model.
On the front end, OrCAD sports a new graphical design difference viewer that can show both logical and graphical changes to a schematic. New advanced annotation capabilities provide much more control of your design annotation process. You can assign reference ranges hierarchically at block, page, and property-block levels, either with prefixes or generic rules. You can also perform selective annotation. All the new annotation features are fully integrated with auto-referencing.
Altogether, the enhancements to Allegro and OrCAD form a significant upgrade to the company’s PCB offering. With the competition heating up in board design, demonstrating improvement in time-to-market, design productivity, and risk-reduction will be key to winning the next wave of new design seats.