feature article
Subscribe Now

Revamped Digital IC Flow

Cadence Launches Innovus

It’s a familiar tale of woe: new silicon process nodes are creating an extreme burden for design tools.

When I say, “familiar,” it’s not just because everyone is bemoaning the current state of affairs, what with FinFETs and multiple patterning and other new features creating innumerable vexations. No, it seems that this happens after every few advances: the improvements made to nullify the last set of hurdles run out of steam in the face of the latest set of new hurdles. And so tools get rolled again.

The product of the tools – a correct mask set – hasn’t changed; the ways we get to that mask set have changed over and over. And continue to do so.

Case in point: Cadence has refreshed their digital flow in a big way. So much so that they’ve changed the branding: Encounter is giving way to a new platform called Innovus*. There will be no forced tool transition – they’re going to ease this one for a while. But, to be clear from a positioning standpoint, Innovus is inheriting the Encounter mantle, even though they’ll coexist for some indefinite time.

What has changed in Innovus? How about the entire flow? For the longest time, their tried-and-true flow went as follows:

  • Start with a coarse placement, done with priority on managing signal routing congestion.
  • From that initial placement, go back in and do fine placement, making adjustments to improve performance, power, and area (PPA).  These optimizations might, at one time, have been done with simplified analysis tools to save processing time, but, increasingly, sign-off tools have been available for this.
  • In order to foster faster processing, make sure not to let blocks get too big. Fracture or add new hierarchy levels if necessary.
  • Finally, validate the finished design with sign-off simulations. If sign-off tools hadn’t been used during optimization, then discrepancies might result in design iterations as more accurate calculations revealed issues. This has increasingly disappeared from the flow for all the major vendors.

“So, what’s wrong with that flow?” you may ask. Actually, a number of things. Due to the primacy of congestion in the initial placement, PPA gets a back seat, and any optima achieved are likely to be local. Power, in particular, has become so important that it can’t be completely subordinated to congestion.

Older algorithms also tended to treat all metal layers (well, maybe not the topmost fat power layers) the same. Signals that are particularly performance- or power-sensitive would perform better with close-in routing on lower layers, with fewer vias and jogs.

To make matters more complicated, features that used to coexist on the same layer are now likely to be split up: double (or more) patterning results in a partitioning, or “coloring,” of features, so that the full set is spread over two or more masks. Said using modern parlance, older algorithms aren’t “color-aware,” and so they can’t deal well with this.

Hierarchical design is useful for a few reasons. Historically, it’s been hard to process an entire flat design in a reasonable time. But, even if you had infinitely fast processors, hierarchy can still help to make a design more understandable by illustrating logical chunks. It’s particularly helpful when different chunks are designed by different engineers on a team.

The problem is, those real-world processing-time limitations required fracturing the design further than might otherwise have been desirable, resulting in more levels and more blocks at the upper levels. Placing blocks is less efficient than placing “flat” (with all hierarchy boundaries eliminated), since you can’t take advantage of opportunities to optimize across block boundaries. So a design with more blocks than necessary will give a suboptimal result.

That’s the old way of doing things. Cadence’s Innovus flow works differently. The primary point is that there’s only one placement run now, done by what they call their GigaPlace engine. Unlike the old heuristic-based placement algorithms, GigaPlace is equation-based, providing a more general solution. It works with the assistance of Quantus, their newer sign-off extraction engine, Tempus, their newer sign-off timing analysis engine, and Voltus, their newer sign-off power integrity engine. They also use their Flex H-Tree engine for the clock trees. And GigaPlace is color-aware.

The placement step is followed by tweaks to improve dynamic power (using GigaOpt – Cadence uses a lot of brands starting with “Giga”… I keep waiting for Kramer to insist that some product be named “GigaGiddyup!”) – and to insert and optimize the clock tree using CCOpt. Once the placement is stable, then their NanoRoute tool pulls it all together by connecting the dots.

Innovus also gives you more freedom in choosing your hierarchy. That’s because it can flatten everything out before processing. It means that you can set up your hierarchy in a logical or functional fashion without worrying about the processing implications – the hierarchy is now just for you and disappears (or largely disappears – you can keep large blocks) for processing. It also means that cross-boundary optimization is no longer a problem: most or all of the boundaries are gone when the algorithms start their work.

You might reasonably object that this throws us right back into the “too much to process” problem that hierarchy was originally intended to solve. But there’s another change to the tools that we haven’t addressed yet: everything has been structured to facilitate massively parallel processing – whether multi-threading inside a single processor or distributed processing using farms of servers. Yeah, if you tried it all on a single machine for a big chip, you’d probably be in trouble. Divide-and-conquer makes it manageable – they claim significantly faster turn-around-time (TAT) compared with the older, supposedly faster hierarchical approaches.

And even though they’re flattening out much of the design, they say that they are still able to protect against engineering change orders (ECOs) rippling farther into the design than necessary; they reassured that they still have an effective ECO flow for those last-minute tweaks.

That said, they also claim that less manual futzing is necessary to improve upon automatic results – the tools churn out results that can meet or even exceed the design requirements. Yeah, I’m sure you could challenge this by creating outrageous requirements, but here’s the thing: if the tool can’t do it, can you do better manually?

Cadence is betting not – or at least not very often. If that plays out, the good news is that, when the tool is done, you’re done, saving the design time that you might otherwise have spent trying to improve the results by hand and minimizing the number of ECOs. (Well, the ones not generated by marketing at the last minute, anyway…)

Finally, the old flow featured a succession of tools, each with its own interface. Innovus pulls all of the steps together under a single, scriptable user interface.

While the focus is digital, it can also work with Virtuoso for analog blocks. Virtuoso must still be used to implement analog circuitry, but analysis results for a mixed-signal design can be viewed in Virtuoso or in Innovus.

Overall, they’re claiming 10-20% improvement in PPA results and as much as 10 times faster TAT or bigger capacity. Of course, processing power is going to depend on how many servers you have available to share the load, but even “just” doubling TAT can be a pretty useful achievement

Now, you might ask, “10 times faster compared to what?” In this case, they had a set of lead customers that have had the tool for 6-9 months, and the comparisons are to whatever their incumbent flow was – might be an older Cadence tool, might be a competitor. In some cases, it was a competitor – and the customer switched to Innovus.

Presumably Innovus has been engineered to take us through several future process nodes. Of course, just as past tools and algorithms have run their course, so will the current incarnation of Innovus – eventually. Bets are being taken at the front counter as to which node will force the next major change.

 

*During the briefing I took, I heard both “IN-no-vus” (reminiscent of “innovate”) and “in-NOH-vus” (sounding more like “nova” or new). So… take your pick; they’re happy with either one. (They’d probably prefer it if you said it while writing a check.)

 

More info:

Cadence Innovus

 

5 thoughts on “Revamped Digital IC Flow”

  1. Pingback: look at more info
  2. Pingback: Mengulik Strategi

Leave a Reply

featured blogs
Nov 25, 2020
It constantly amazes me how there are always multiple ways of doing things. The problem is that sometimes it'€™s hard to decide which option is best....
Nov 25, 2020
[From the last episode: We looked at what it takes to generate data that can be used to train machine-learning .] We take a break from learning how IoT technology works for one of our occasional posts on how IoT technology is used. In this case, we look at trucking fleet mana...
Nov 25, 2020
It might seem simple, but database units and accuracy directly relate to the artwork generated, and it is possible to misunderstand the artwork format as it relates to the board setup. Thirty years... [[ Click on the title to access the full blog on the Cadence Community sit...
Nov 23, 2020
Readers of the Samtec blog know we are always talking about next-gen speed. Current channels rates are running at 56 Gbps PAM4. However, system designers are starting to look at 112 Gbps PAM4 data rates. Intuition would say that bleeding edge data rates like 112 Gbps PAM4 onl...

featured video

Product Update: Broad Portfolio of DesignWare IP for Mobile SoCs

Sponsored by Synopsys

Get the latest update on DesignWare IP® for mobile SoCs, including MIPI C-PHY/D-PHY, USB 3.1, and UFS, which provide the necessary throughput, bandwidth, and efficiency for today’s advanced mobile SoCs.

Click here for more information about DesignWare IP for 5G Mobile

featured paper

Streamlining functional safety certification in automotive and industrial

Sponsored by Texas Instruments

Functional safety design takes rigor, documentation and time to get it right. Whether you’re designing for the factory floor or cars on the highway, this white paper explains how TI is making it easier for you to find and use its integrated circuits (ICs) in your functional safety designs.

Click here to download the whitepaper

Featured Chalk Talk

ROHM BD71847AMWV PMIC for the NXP i.MM 8M Mini

Sponsored by Mouser Electronics and ROHM Semiconductor

Designing-in a power supply for today’s remarkable applications processors can be a hurdle for many embedded design teams. Creating a solutions that’s small, efficient, and inexpensive demands considerable engineering time and expertise. In this episode of Chalk Talk, Amelia Dalton chats with Kristopher Bahar of ROHM about some new power management ICs that are small, efficient, and inexpensive.

Click here for more information about ROHM Semiconductor BD71847AMWV Programmable Power Management IC