Kato, Robin, Watson, Tonto, Spock, Barney, Hutch, Higgins, FPGAs – everyone knows the importance of a top-notch sidekick. We’ve seen FPGAs teamed up with countless heroes, parked next to just about every type of device you can imagine. And FPGAs are steadfast in the fulfillment of their duties – bridging the logic, driving the interfaces, accelerating the processing, scaling the video, integrating the peripherals – no task is too unglamorous for the hard-working FPGA – and it often manages several of these at once.
Today, if you’re designing a custom chip, chances are you’ve already considered putting an FPGA next to it. And that’s before your custom design is even done. There are just too many variables in a new design, and you have to assume that you won’t have them all nailed down before you tape out. There may be some standards that aren’t solidified yet (and you certainly don’t want to wait for standards committees to finish their seemingly-endless deliberation before you proceed with your design). There may be multiple variations of your design that require different external interfaces. There may be modems that need to be reconfigured for various flavors of communication. There may be DSP or other processing tasks that require hardware acceleration. In fact, this paragraph could probably go on for the rest of the article just listing all of the reasons an FPGA paired with a custom chip is a great idea, and often a necessity.
Still, the hero/sidekick setup isn’t the ideal configuration in electronics systems. After all, the whole point of making a custom chip is to integrate and consolidate. You want the best performance, the smallest form factor, the lowest power consumption, and the least BOM cost. And none of those goals are well served by parking an expensive, power-hungry FPGA (along with its supporting circuitry) right next to your new, shiny, custom-designed chip, ASSP, or SoC.
What you really want is to be able to put some FPGA fabric IN your custom chip design. Then, you’d have all the advantages and security of a sidekick, without actually having one on the payroll. You already know where it goes. It sits next to that part of the design that keeps you awake at night – policing the border between the things of which you’re certain and the things you fear.
But FPGA companies don’t offer their fabric as IP. And, even if they did, you’d be out of luck with a bunch of LUTs and no tools to make them useful. At least until Flex Logix came along.
Flex Logix has just come out of stealth mode, and they are offering exactly what you need – FPGA fabric that can be woven smoothly into your custom chip design, and a robust set of tools that can help you use it when the time comes.
Ah, we hear you out there: “How do you put FPGA fabric on a custom device? You’ll never get the tools tuned to all the vagaries of the custom FPGA fabric.”
Yep, that would be a problem. Fortunately, Flex Logix thought of that already – and they’ve got a clever solution. Flex Logix EFLX cores come in two sizes, and each of those can be tiled together to make larger arrays of FPGA fabric. The tools just need to know which tiles you’re using and what arrangement you’ve put them in (1×2, 2×2, etc. – the company says you can make up to 7×7 arrays of their 2,500 LUT tile). Then you’ve got all the tool power you need – tailored for your custom FPGA-IN-a-chip.
Those of you with some knowledge of FPGAs and custom chip design may have spotted another pretty major problem as well: FPGAs require a LOT of metal layers to achieve the routability that is needed to make them useful. If the device you’re planning doesn’t include that many layers, it would take a major (and expensive) upgrade of your design to handle the overhead of adding conventional FPGA fabric to the mix. But Flex Logix has thought of that one as well. They have developed a new and novel type of hierarchical interconnection network that the company claims can cut interconnect resource requirements by “50% or more” – reducing the number of metal layers required, in the process. At the same time, the more efficient interconnect reduces power consumption, improves performance, and makes timing closure easier.
Flex Logix licenses EFLX using a conventional IP model and supplies a full set of tools for populating the FPGA design. The company is headed up by former Rambus CEO Geoff Tate, who knows a thing or two about the IP business. The company says that adding a 2,500 LUT core to a design should add only 15 cents to the total manufacturing cost of your device. That’s FAR less than you’d expect to pay for an FPGA sidekick. And, you’ll get serious benefits in board complexity, form factor, power consumption, and performance. You’ll also eliminate the need for all those external IOs that would have connected your custom chip to the external FPGA (and all the PCB traces that would have carried those signals).
We can see a number of use scenarios for EFLX. First, there are those of you working on ASSPs who don’t want to wait for every emerging standard to be completely nailed down before you finalize your chip design. If you don’t have to wait for standards to finalize, you can be earlier to market – and we don’t need to repeat the enormous economic benefits of that here. Or, you could more easily make a single ASSP to serve multiple markets or variations. By combining what would have been multiple tape-outs into one, you save approximately a gazillion dollars of NRE and hassle.
Or, if you’re working on an application like software-defined radio, you could use the FPGA fabric to swap among multiple modems on the fly. That’s something you can’t really accomplish easily with a stand-alone custom chip. If you’re in the video business, you could drive various display scales and resolutions with a single device – customizing the FPGA fabric to match up to various display standards.
If your application requires compute acceleration, the FPGA fabric could be reconfigured to implement various custom accelerators. The major FPGA companies are obviously tackling this head-on already with devices like Xilinx Zynq and Altera SoC FPGA. But if your application requires custom hard logic that doesn’t happen to be on those devices, EFLX will allow you to design those same benefits into your custom IC.
There is also an interesting element of “who does the customization?” Obviously, for many applications, you’d use the FPGA fabric to customize your design before you ship chips to your end customers, or before your system design teams take the chips and run with them. Of course, system designers could then make the system field-upgradeable, so you could fix that one thing you messed up even after the systems are installed in customer sites.
But it also is possible that you could ship devices with the intent that the end-user/system designer would do the customization themselves. In that case, Flex Logix would need to supply the appropriate tools to your end customer. While this model entails the most complicated design and support scenario, it does open up a rich set of new possibilities.
It will be interesting to see what kind of applications adopt Flex Logix IP first. There is a very wide range of applications and industries that could obviously benefit from this IP, and the company appears to have done a good job thinking through the traps that would make FPGA fabric integration into a custom design a challenge. We’re anxious to hear how it goes.
10 thoughts on “Put an FPGA IN It”
Adaptive Silicon re-born?
Excellent observation, Mr Selwood. However: they’re much less than Adaptive Silicon. They haven’t even scratched the surface on the challenges to successfully executing such designs. I would know – I was part of the AS effort.
A French company called Menta has a similar technology, an FPGA as IP block in an ASIC.