feature article
Subscribe Now

Max 10 Kills the CPLD

Altera Redefines Non-volatile FPGAs

The venerable CPLD (Complex Programmable Logic Device), forefather of today’s flourishing FPGA and programmable logic industry, died peacefully in its sleep last night of natural causes. No memorial services are planned. The CPLD is survived by an incredible array of modern, capable devices that take the concept of programmable hardware to places never envisioned by the stately senior sum-of-products statesman.

If you visit the Wikipedia page for “CPLD” you will find a picture of an Altera MAX device (EPM7128), a 2,500 gate-equivalent, 128 macrocell “second generation” CPLD (or “EPLD” as the company was spinning it in those days) which, according to the datasheet, was capable of implementing “complete system-level designs.” That is, of course, if you were designing a “system” that could be implemented in well under 2,500 gates, was all digital, and had a 2-digit number of IOs.

Now, Altera has unveiled their new and incredibly capable “MAX 10” family, and they have finally dropped the CPLD ruse. MAX 10 is a non-volatile FPGA. In truth, MAX devices have been FPGAs for the better part of a decade now. Way back in 2004, when the company announced “MAX II CPLDs” they quietly admitted that, contrary to the name, the devices were actually built as an array of LUTs (SRAM-style), with an on-chip flash memory that allowed almost instant on, single-chip operation (it takes only a few milliseconds for the device to configure itself from on-chip flash, rather than relying on off-chip configuration at startup like a conventional FPGA.) 

The new MAX 10 brings that same architecture to the future. MAX 10 is a highly capable FPGA with an on-chip flash configuration memory. For the first time, the on-chip flash is capable of dual configuration. That is, it can hold more than one configuration of the FPGA. Dual configuration brings a host of new usage models to the table that we haven’t yet seen on a non-volatile FPGA, such as fail-safe upgrades, where the “factory” configuration can be retained in one memory partition while a new upgrade is loaded and verified, without risk of corrupting or replacing the previous configuration. There is also a third, “user” flash memory block, which brings up an interesting set of additional ideas for applications. 

MAX 10 brings densities up to 50K logic elements, a quantum leap for SRAM-based non-volatile FPGAs. Lattice’s largest MACH XO3 device, by comparison, weighs in at 6.9K logic elements. But MAX 10 brings a lot more than LUTs to the party. The new family includes analog blocks (ADCs and temperature-sensing diodes), which enable the devices to be used in system monitoring applications. And, with that kind of density, MAX 10 can easily integrate an Altera Nios II soft-core embedded processor, turning it into a non-volatile (almost) instant-on high-performance SoC. This time, 12 years later, it actually CAN integrate “complete system-level designs”… at least for a sufficiently modest definition of “system.”

Nios is a full-blown 32-bit processor, and, combined with the connected FPGA fabric, it can probably teach your favorite MCU a trick or two. Instead of shopping for just the right MCU with the right combination of features, you can use MAX 10 to create your own, just to your specifications. Because MAX 10 is “instant on” (and in this case, “instant” means less than 10ms for the chip to configure itself from on-chip flash), a wide range of system startup, system monitoring, power sequencing, and system management applications are within easy reach – in markets ranging from automotive to industrial to communications. Fast boot-time operations like driver-assist cameras could be easily supported with the fast startup capability.

On the IO front, MAX 10 delivers up to 500 user IOs, and it includes a DDR3 external memory interface for high-performance commodity external storage. This is a considerable amount of IO for a CPLD-class device. All that IO would also make MAX 10 great for a range of bridging applications. 

If you’re concerned about board space, MAX 10 is available in packages as small as 3x3mm (not with all 500 IOs, of course), and, since it has an integrated power regulator and on-chip oscillator, along with the aforementioned flash and boot configuration circuitry, you won’t be needing a lot of other devices to support the FPGA.

Since the logic cells (LUTs) are built with SRAM-style logic and configured from flash, you don’t have to pay the “flash penalty” of performance of the FPGA fabric.  You’ll get the performance you’d expect in a conventional SRAM FPGA in a device that behaves like a non-volatile one. 

MAX 10 is fabricated on TSMC’s latest 55nm flash process. This means that Altera’s three major lines – Stratix 10, Arria 10, and MAX 10 – are all fabricated on different processes: Stratix 10 on Intel’s 14nm Tri-Gate process, Arria 10 on TSMC planar 20nm, and MAX 10 on TSMC 55nm flash. Interestingly, we have not yet heard any hint of a “Generation 10” Cyclone family, but there seems to be a sufficiently interesting gap in the Altera line where one could show up.

One way this launch is particularly interesting and unusual is the timing. MAX 10 is available today, along with tools, dev kits, and reference designs. This is in sharp contrast to the “normal” process of announcing a new FPGA family where we see nothing but PowerPoint slides for many months after the announcement. Altera apparently sees MAX 10 as a “design it in and use it right now” kinda’ product, compared with their families such as Stratix, which have a long design-in and procurement cycle. 

We haven’t seen a new MAX family from Altera in a number of years, so this is a welcome refresh. Xilinx seems to have quietly dropped out of the race for this class of devices, and Lattice Semiconductor’s similar-class devices are much smaller and less feature-laden than this new Altera line. It’s pretty exciting to see how far the ‘CPLD’ class of programmable logic has come in the past decade – even though the vast majority of attention has gone to the bigger, faster, more glamorous devices. We think MAX 10 is pretty exciting all on its own.

15 thoughts on “Max 10 Kills the CPLD”

  1. I am missing where this new Altera series fits price wise. Lattice never went to the biggest – but instead a market not so much served by A and X. I have been selling against A and X – or more positively, finding the right niches for Lattice.
    So Lattice must be happy for Altera to move up – leaving even more space for Lattice?
    Max10 kills CPLD – might have to be rephrased into- Altera now has a faster replacement for the old Altera CPLDs, following the same path as Lattice has with the XO and XO2 series years ago.
    AND there are still niches for CPLDs, they are not dead – there is even TTL and gates around after 40 years …
    The editorial filter was a bit loose letting too much Altera marketing through I think.

  2. @juergenuk You can buy a development board with the largest part for $50. The smallest part is 25 times smaller and yet is still large enough to fit a NIOS processor and 16 DSP units plus logic left over.

  3. @Steve DevKits are mostly subsidized, so does not count. I meant designed in, product cost, how does it compare Altera – Lattice – Microsemi – Xilinx imlementation ( sorry if I forgot some ). I know there are many variants – any example/volume appreciated.
    I am not trying to be negative, just the facts please.

  4. Ouch! Marketing filter… I am shamed. I thought I was a little snarky even, a couple of places. In my defense, the dead CPLD part was completely original. I have always thought it funny that there is a whole class of FPGAs that we still pretend are CPLDs, when sum-of-products hasn’t been a viable way to design a new chip for quite a long time. In reality, nothing has changed here except marketing. Altera is finally coming clean and calling the device an “FPGA”.

    One thing I did fail to mention in the article is that the device has DSP blocks. That’s also unusual for this class of non-volatile device, I think.

    I’ll see if I can get an answer for estimated volume price range. As you probably know, FPGA pricing is a bit like airline ticketing… “It depends”. They probably come in somewhere between $0.25 and $100, depending on when you book, how many frequent-designer miles you have, and whether there is a PCB baggage fee.

  5. Kevin, nice original and kind of funny writeup… However, I use an old Xilinx CPLD that does a nice job of replacing lots of popcornn logic (or is that jellybean?) for around $1.00… Looks like these parts cost (in onsies anyway) around $25.00 so I doubt they are going to replace my small-ish CPLD requirements any time soon.

    But, I have been thinking about moving up to a slightly larger Lattice CPLD with twice (64) the elements for around the same price.

    Does Altera have anything in this area still or is it the all or nothing FPGA market now for you guys ? I don’t see the CPLD market drying up yet until Flash based PGAs prices come down a bunch. I’d love for that to happen !


  6. Pingback: gvk biosciences
  7. Pingback: YouJizz
  8. Pingback: agen bola terbesar
  9. Pingback: colarts Diyala

Leave a Reply

featured blogs
Jun 6, 2023
Learn about our PVT Monitor IP, a key component of our SLM chip monitoring solutions, which successfully taped out on TSMC's N5 and N3E processes. The post Synopsys Tapes Out SLM PVT Monitor IP on TSMC N5 and N3E Processes appeared first on New Horizons for Chip Design....
Jun 6, 2023
At this year's DesignCon, Meta held a session on '˜PowerTree-Based PDN Analysis, Correlation, and Signoff for MR/AR Systems.' Presented by Kundan Chand and Grace Yu from Meta, they talked about power integrity (PI) analysis using Sigrity Aurora and Power Integrity tools such...
Jun 2, 2023
I just heard something that really gave me pause for thought -- the fact that everyone experiences two forms of death (given a choice, I'd rather not experience even one)....

featured video

Synopsys Solution for RTL to Signoff Power Analysis

Sponsored by Synopsys

Synopsys’ industry-leading power analysis solution built on PrimePower technology that enables early RTL exploration, low power implementation and power signoff for design of energy-efficient SoCs.

Learn more about Synopsys’ Energy-Efficient SoCs Solutions

featured paper

EC Solver Tech Brief

Sponsored by Cadence Design Systems

The Cadence® Celsius™ EC Solver supports electronics system designers in managing the most challenging thermal/electronic cooling problems quickly and accurately. By utilizing a powerful computational engine and meshing technology, designers can model and analyze the fluid flow and heat transfer of even the most complex electronic system and ensure the electronic cooling system is reliable.

Click to read more

featured chalk talk

Nexperia Energy Harvesting Solutions
Sponsored by Mouser Electronics and Nexperia
Energy harvesting is a great way to ensure a sustainable future of electronics by eliminating batteries and e-waste. In this episode of Chalk Talk, Amelia Dalton and Rodrigo Mesquita from Nexperia explore the process of designing in energy harvesting and why Nexperia’s inductor-less PMICs are an energy harvesting game changer for wearable technology, sensor-based applications, and more!
May 9, 2023