28nm is a calm, mature node. Sure, everyone was excited when it was the first to reach modern price, performance, and cost levels. We applauded when ARM processing subsystems were integrated into 28nm FPGAs, creating a new class of device. And there were accolades when 28nm debuted interposer-based 2.5D packaging techniques. There is even a nice page in the scrapbook where 28nm SerDes transceivers hit 28Gbps speeds – a nice 28/28 symmetry that made everyone feel all warm and fuzzy.
We all know and love 28nm. It’s out there – proven and in full production, making our real-world designs really work today. It’s great! You really can’t go wrong with any of Xilinx’s or Altera’s robust 28nm offerings – from cost-optimized, higher-volume Kintex and Arria chips up to the biggest, fastest, most feature-laden Virtex-7 and Stratix V devices, 28nm FPGAs have you covered.
Unlike that crazy FinFET kid. Yeah, he’s been nothing but trouble from the start. First, he ran away from home with Altera – who took their high-end Stratix 10 project from TSMC over to Intel to get its FinFETtedness going on their upcoming 14nm TriGate (Intel’s name for FinFETs) process while Xilinx stayed back at TSMC to fit their fins on TSMCs new 16nm node. Then, a war of rumors, speculation, and press releases followed as both companies slowly dialed back delivery expectations for the 14/16nm Tri-Gated FinFETty development project nightmare.
Before FinFET-having FPGAs are in any kind of volume production, the parents are going to go through hell for sure. Despite all the potential for dramatically improved power consumption statistics, crazy densities, and performance like we’ve never seen before, FinFET FPGAs are proving to be rebellious, spoiled little brats. They may or may not set the world on fire with their amazing capabilities, but nobody expects them to settle down and get real jobs any time soon. They will most certainly be late, expensive, and temperamental, and they will probably be viable only for those with bleeding-edge bandwidth and performance requirements who simply don’t have any other options.
Luckily, we’ve still got reliable-old 28nm out there punching the time clock, bringing home the bacon, and making the parents proud. Those work-proven 28nm FPGAs can handle just about anything we want to throw at them, and that’s surely a relief with all that madness going on with the next node… Wait. We forgot one. 14/16nm actually ISN’T the next node. 20nm is in there… doing what?
Hi there, 20nm FPGAs! We’re sorry we left you out of the holiday card family portrait. And don’t take it personally that we were one chair short at the dinner table. We just got distracted with all your younger brother’s FinFET antics and lost count. We do hope your tapeout and dance recital went well, though. Sorry we got the dates mixed up and missed them. We really do still care.
Yes, folks, even though it’s easy to forget, both Xilinx and Altera have 20nm families as well. The first examples of both companies’ 20nm planar TSMC-fabbed FPGAs are now rolling off the assembly line. Xilinx has thrown a wide marketing net around both 20nm planar and 16nm FinFET offerings with their “UltraScale” branding. Rather than tying the UltraScale name to a single process/family as they have before, they’re using UltraScale as an architectural lynchpin that encompasses both 20nm planar and future 16nm FinFET device families. It might be 20nm, it might be 16 – it scales. It’s UltraScale.
Xilinx announced that the first customer samples of their smaller, Kintex UltraScale devices based on 20nm technology were shipping back in November, with broader sampling early this year. The first samples of their 20nm Virtex UltraScale devices shipped in May. Neither family is in volume production yet, but you can get started designing with the Vivado tool suite today, and samples of some sizes of both Kintex and Virtex are available.
Altera is also shipping engineering samples of their first 20nm Arria 10 devices, and they have today announced the release of “Quartus II Software Arria 10 Edition V14.0” which (obviously) supports the new devices. Altera decided to skip 20nm with their high-end Stratix line, instead relying on 28nm Stratix V to carry them over until the rowdy 14nm Intel-fabbed Tri-Gate/FinFET Stratix 10 family comes online sometime in 2015.
20nm may seem a little underwhelming and forgettable for two reasons. First, it will be the last node fabricated in the traditional planar CMOS. Below 20nm, the incremental ROI with planar devices really tapers off. With 20nm, instead of the usual “double everything” from Moore’s Law, we get more like “1.6X everything.” Now, 1.6X is nothing to sneeze at, but with each node costing exponentially more than the previous one, the cost/benefit curves are converging at an unsustainable rate.
Of course, none of that has stopped the usual marketing bluster between the two companies. Both players claim their devices are bigger, faster, and more capable than those of the other. Both companies assure us that their tools are more robust and can compile our designs more quickly. All of the claims are carefully tailored to be technically true but are misleading-by-omission at best. When you hear that a device is the “fastest” FPGA “produced today” – what does that really mean? And, does “fastest” refer to fabric Fmax? SerDes bandwidth? DSP aggregate GMACs or GFLOPs? First to hit the ground when dropped from a tall building?
With all the claims from both vendors, you need to look past the press-release headlines and decide what actually fits your particular application best. There are significant differences in the two vendors’ chips, tools, IP, and other factors that make one or the other better for different applications and project timetables. There is no blanket marketing (or analyst) statement that can do the job of choosing your FPGA for you, unfortunately.
Beyond 20nm, FinFETs give us an incremental bump beyond the usual scaling benefits. So – the leap to 14/16nm will have closer to the usual “2X” Moore’s Law gain. And, despite the fact that Moore’s Law is “slowing down,” the 14/16 node is following closer on the heels of 20nm than the usual 2-year cycle. Even though 20nm FPGAs are first sampling this year, it will not be the normal two-year wait before 14/16nm devices begin sampling.
So, 20nm has less incremental benefit than usual, more capital investment required than usual, and a shorter life span between nodes than usual. All of that conspires to cement its “middle child” status, and explains why both Xilinx and Altera continue to extol the virtues of long-lived 28nm devices while promising the moon and stars from upcoming 14/16 FinFET FPGAs. Oh, and, by the way, they both have 20nm devices too.