There’s promise, and then there’s reality.
The promise of FinFETs has been one of higher performance with lower power than would have been possible if we had stayed on the same track as before and tried to keep scaling. This promise seems, more or less, to be realizable as companies start integrating these new devices into their aggressive-node designs.
The accompanying reality, in this case, has to do with all of the other details that you get along with the benefits. In other words, those benefits come at a price – and one of the costs has to do with power noise. Ansys has released a new version of their Redhawk power analysis tool (you may think of them as Apache, but they’re now owned by Ansys), and much of what they’ve done in this version has been due to the needs of designs incorporating FinFETs.
A few of the new challenges arise specifically because of the unusual geometry of the FinFET. Instead of a planar transistor, you’ve got a vertical fin acting as the channel, surrounded on three sides (in current implementations) by a gate. This in and of itself brings with it some unique issues.
But other issues arise, not specifically due to the physical configuration of the FinFET, but rather as a result of the performance that it unlocks.
Ansys talks about three different areas of impact for the power network: noise and sensitivity, electro-migration, and electrostatic discharge (ESD, aka static electricity zaps).
The basic benefit of the FinFET is higher speed in a smaller space. This involves higher currents (as much as 25% higher peak levels) switching more quickly, which means more inductive spikes (due to the higher di/dt), which translates to more noise. This is exacerbated by a more complex interconnect network – especially in light of more resistive local interconnect.
At the same time as the circuit is generating more noise, the voltages are dropping, reducing the noise margin. So we’re moving from 100 mV of noise on a 1-V rail to something more like 150 mV on a 700-mV rail – in other words, 10% to 21%, according to Ansys’s numbers.
This leaves far less room for error – meaning that analysis and simulation accuracy have to be higher. Looked at another way, you’ve got more complex circuits – which in and of themselves create a greater analysis computational load – that also have to be done more accurately.
And that’s just considering the chip alone. The package is also part of the power delivery network, and package design matters. Analysis of the package and chip used to be done separately, with a simplified lumped package model delivered to the chip guys for use in the chip analysis. But that gives little insight into problem areas – which might be in the package or on the chip. So Ansys is now doing package-aware chip analysis that combines the detailed package and chip networks for a complete model that can be analyzed and optimized as a whole.
So now you’ve got this huge network that needs to be analyzed more accurately than ever before. And, unlike many other types of simulation, you can’t break the network up for independent analysis of different pieces: In theory, the network must be solved all together and is not well suited to parallelism.
That challenge notwithstanding, Ansys has actually found a way to do distributed computation. It’s still not possible for each computing engine to work completely independently – they still need visibility into what’s happening with other chunks of the calculation – so Ansys has implemented a specific optimized way of partitioning that allows a nominal amount of autonomy for each engine while minimizing the amount of communication needed between processors. This keeps analysis time reasonable even in light of the increased requirements and expectations.
Meanwhile, this isn’t just a matter of currents increasing; they’re increasing at the same time as metal lines narrow down. In other words, the current density is going up. And higher current density means greater risk that those metal molecules will get dragged around, migrating away from where we want them for deposition someplace else.
To make things worse, the FinFET configuration isn’t as good at dissipating power as its planar forebears are. In the past, you had the huge bulk of the underlying wafer as a heat sink to keep the channel temperature down. That channel has now been flipped on its side, and the bulk contacts only the narrow bottom, making it less effective at sucking out the heat. So temperatures may go up, placing further stress on the electro-migration situation – especially when the interconnect now bears a greater share of the heat-sinking role.
Now, you could reasonably look at some of the devices being made today and wonder whether electro-migration is really an issue. So much of today’s electronics are made to last only as long as a two-year cell phone contract or until the next great hype cycle for some new widget starts. After all, these aren’t the high-power devices of the ‘90s and 2000s that were populating the communications infrastructure and had to last 15 years or so. But, at these performance levels, Ansys says that electro-migration can be a concern even for the 3-5-year timeframe. So they say that careful analysis is needed to ensure that problem spots are identified and fixed.
Finally, ESD. And this one blew my mind a bit. We’ve had ESD solved for years, relying on the junctions in planar devices that provide a natural parasitic SCR (silicon-controlled rectifier – a PNPN junction) that “snaps back” when zapped with a high voltage, allowing a diode to shunt away the excess energy before it damages more delicate parts of the circuit. Such ESD protection has been a well-studied phenomenon, and, having been solved, it’s not something that designers want to go back and revisit each time they do a design.
Problem is, part of the SCR is the bulk silicon. The part that’s no longer sitting right under the device channel because the channel is now up on its side. In other words, we no longer have this natural SCR with FinFETs. You could argue that planar transistors could be used just for ESD protection, but, at least as far as Ansys is aware, no foundry is supporting a mixture of FinFET and planar devices. One FinFET means all FinFET.
This gets coupled with increasingly complex power architectures having various internal rails and islands that may or may not be powered up at any given time. Each of these islands may need its own ESD protection embedded in the island – unlike past circuits, where they could be positioned all on the periphery of the die where the signals and power entered the chip. In response to all of this, Ansys includes beefed-up ESD integrity analysis as part of the sign-off suite.
All in all, Ansys’s point is that they’ve had to ratchet up the capabilities of their latest Redhawk version so that these FinFET-induced realities don’t neutralize the FinFET promise of higher speed with lower power in a smaller area.
7 thoughts on “Challenged By FinFETs”
We’ve seen some FinFET challenges that Ansys’s Redhawk deals with; are there others as well?
As always Bryon, you do good coverage of the technology issues, not just a tool. In doing so you make hearing about the tool an important part of the solution. Excellent piece!