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Synopsys Adds DSP Features to ARC Processors

New EM5D and EM7D Compete with Rival’s Cortex-M4

Always wanted an ARM Cortex-M4 processor but didn’t like the popular instruction set and massive software support? Well, friend, your ship may have just come in. Step right this way and shake hands with the ARC EM5D, the latest miniature CPU core from Synopsys. Now with more DSP!

ARC is the in-house CPU arm (hah!) of Synopsys, a company normally associated with EDA tools. The ARC processor is more popular than most people might think: the architecture has nearly 200 licensees (more than ARM and MIPS put together) and is on track to ship 1.5 billion units this year. The ARC processor is small, cheap, and configurable. You can add and subtract features, either from a menu of options or from your own imagination. The CPU’s register set, instruction set, buses, and functional units are all modular and adjustable, which allows SoC designers to twist, tweak, and dial-in just the CPU design they want for their project. The downside of all this configurability, if any, is that there’s not a lot of canned software for ARC processors. It doesn’t run Android or have a big online app store. But if all you want is a CPU to crank through your own in-house code, an ARC processor is one of the cheapest and easiest ways to get that done.

New this week are the EM5D and the EM7D, smaller sisters to the existing HS family of ARC processors. The EM twins have basic three-stage pipelines and a bunch of new DSP-related features. The ’5D and ’7D are to the ARC product line what the Cortex-M4 is to ARM’s.

What’s the difference between the ’5D and the ’7D? The former uses closely coupled memories (i.e., SRAM) while the latter has caches. Broadly speaking, the ’7D will deliver the higher performance of the two, for faster chips that can benefit from instruction and data caches.

The D in the product names is the real news. It betokens a new set of DSP extensions that add something like 100 new instructions, and several new registers, to what was otherwise a plain-vanilla CPU design. Just look at all you get: SIMD instruction execution, a single-cycle multiplier, matrix arithmetic, 80-bit MAC, square root, and other goodies. And if the 100+ new instructions aren’t enough, you can always add your own.

The DSP extensions allow ARC to play in other reindeer games, such as voice-activated devices, motor control, or sensor aggregation. Its heretofore rudimentary instruction set meant ARC wasn’t really well suited to anything but basic C code tasks. That was fine – remember those 1.5 billion units – but it left out a big chunk of the market that was being serviced by little MCUs with DSP-like aspirations. Archrival Tensilica has had DSP pretensions for a while, and 500-lb. gorilla ARM added its DSP features years ago. That put Synopsys, and ARC, somewhat in the back seat.

No more. Synopsys says the EM5D and ’7D can now process digital signals with the big kids, citing a benchmark based on the “TrulyHandsFree” algorithm from Sensory that shows ARC spanking its (doubtless hand-selected) competitors.

Over on the integer side, the EM5D/7D deliver about the same integer performance as a MIPS, ARM, or Tensilica processor core. That’s not too surprising, since the much-maligned Dhrystone benchmark is well understood, easily optimized, and fairly generic. Any processor that doesn’t make par on Dhrystone probably has something wrong with it.

But ARC’s advantage, according to Synopsys, is that it cranks out that performance using a lot fewer transistors. The company figures its EM5D uses about half as much silicon real estate when compared to a MIPS MicroAptiv, a Tensilica Mini108, an ARM Cortex-M4, or an ARM968. While that may be true, Synopsys lets you strip the EM5D to the bone, leaving out registers, instructions, and entire functional units that you don’t need, and – here’s the point – that don’t affect Dhrystone scores.

Is that cheating? Not at all. In fact, that’s one of the very greatest charms of the ARC architecture. It’s modular and configurable, and you build in only what you need for your particular chip. Don’t need DSP features? Chuck ’em. Don’t want all 32 registers? Slash it down to 16. Narrow data buses good enough for you? Go ahead and save the space. ARC is all about options, and Synopsys allows you to make your own tradeoffs. Fortunately, most of those adjustments don’t affect Dhrystone benchmark scores, so the “MIPS per millimeter” metric looks pretty good for the guys from Mountain View.

Power consumption naturally tracks transistor count and die area, so ARC’s MIPS-per-milliwatt ratio is also very flattering. Granted, this may not play out in your actual configuration, but that’s your call. A generously optioned EM5D occupies just 0.03 mm2 of silicon (in 40nm LP, according to Synopsys), which is approximately … uh…  nothing. At 500 MHz, it consumes about 3.5 mW, which is also in the realm of rounding errors. Bottom line, the EM5D/7D CPU core is not going to be the biggest part of anyone’s chip. Hey, take two! They’re small!

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