As we enter what will perhaps become the “long tail” of Moore’s Law, the traditional battlefield for FPGA companies is shifting dramatically. For most of the history of FPGAs, the main strategic goal was to be “first” on each new process node. If you had FPGAs ready to go on the newest, fastest, densest semiconductor process, you had a significant advantage over your competitor. With each new node, the cost dropped, the power efficiency improved, performance took a leap ahead, and functional density doubled. The combination of those advantages was so substantial that almost nothing your competitor could do would offset a one-node advantage.
Today, however, those new nodes are much harder fought, and the rewards are much more modest. No longer are PPC (performance, power, and cost) automatic “wins” just from moving to the new technology. Leakage current, skyrocketing NRE and mask costs, complex design constraints, and other challenges have forced FPGA companies to make hard compromises among these critical components of semiconductor goodness. Both Xilinx and Altera now have split lines – where “current” devices are not all made on the same process node, and differentiating FPGA product offerings based on process alone has become a losing proposition.
In this new era, other factors are differentiating FPGA companies. Design teams are choosing devices based on available IP, reference designs, specific configurations of hard IP blocks, development boards, packages, and – perhaps most important of all – TOOLS. Design tools are at the heart of every FPGA-based project, and the quality, reliability, ease-of-use, and performance of design tools can literally make or break a project.
Xilinx and Altera, the two big FPGA competitors, have dueled with their tool offerings for years, with some high-stakes, big-drama history to show for it. Altera nearly sank the company just over a decade ago with a disastrous first release of their Quartus tools. The company retrenched and came roaring back, however, and Quartus II – the successor to the ill-fated Quartus – has been giving Xilinx’s aging “ISE” tool suite trouble for years.
Now, however, Xilinx is working to turn the tables with their Vivado tool suite – a ground-up rewrite that took advantage of ASIC-strength technology and modern software development methodologies. Vivado has proven itself quite nicely during its first couple of years, and it’s now beginning to hit its stride as a mature, highly capable design environment.
Now, with the 2014.1 release of Vivado, the company is putting the icing on the cake with a worthwhile bundle of new capabilities. In this latest release, Xilinx has made several “nice to have” improvements – and the first one you’ll notice is an easier, smoother, faster installation flow. Simplified management of installed modules, smaller install images, and an easier installation process are likely to eliminate some of the confusion and frustration up-front.
One of the more interesting things debuting in this version of Vivado is the “Tcl Store.” Tcl (Tool Command Language) is the scripting language on which Vivado itself is based. All of Vivado’s basic underlying functions can be invoked and controlled via Tcl scripts, and Vivado’s user interface is constructed in Tcl. Tcl can therefore be used to easily add to and modify Vivado’s capabilities and features. The Tcl interface opens up a whole world of potentially useful add-ons and plug-ins, and Xilinx has created a “store” – similar to the app stores for smartphones and tablets – that allows the distribution of Tcl modules for Vivado.
The Tcl Store works pretty much like you’d expect, and it is seeded with a small set of useful utilities to help get things started with this first release. The real fun, though, will start if and when the user community begins uploading and sharing helpful Tcl goodies that extend and expand Vivado’s capabilities – and perhaps add some additional domain-specific support for various application areas. So – got a cool Tcl utility for Vivado? Now’s your chance. Get it posted in the store for your big shot at becoming a worldwide Vivado Tcl celebrity – or maybe just to help your fellow designers make a tough job a little bit easier.
One of the lesser-noticed features in Vivado is the tool’s built-in awareness of the configuration of common prototyping and development boards. For many supported boards, Vivado already knows what hardware is on the board and how it’s connected to the FPGA. You don’t have to spend all the effort to describe your board to the tools, and you don’t even have an opportunity to make all the usual mistakes hooking up the correct FPGA pins to the correct peripherals. You can select which of the on-board interfaces you want to use, and Vivado will automatically instantiate the correct blocks in your design – already all wired up to the right pins. While this seems like a simple thing, it is truly a time-saver when you go to populate a dev board with your design.
The biggest challenge in complex FPGA design is clearly meeting all of your design constraints. But perhaps the second-biggest challenge is just getting your constraints specified correctly in the first place – particularly if your design contains large amounts of third-party IP that you didn’t write and perhaps don’t yet understand in detail. Enter Vivado’s new “Timing Constraints Wizard.” The wizard helps you set up your constraints correctly, analyzing your design database and extracting the clocking structure so it can help you identify multi-cycle paths, false paths, paths that cross clock domains, and other typical snags in your constraint setup – perhaps to the chagrin of third-party EDA companies like Blue Pearl, who are working to earn their living by helping you manage some of those same problems.
On the competitive front, Xilinx is offering the first cut at OpenCL synthesis in the HLS portion of this release. OpenCL support is perhaps reactionary on Xilinx’s part, since Altera has been blowing the OpenCL horn for months now. However, starting OpenCL support in HLS signals – even at this early date – that the two companies are taking a fundamentally different approach to OpenCL, and that this difference of approach may even affect the target audience. Altera is clearly going after the software engineer with their OpenCL implementation – targeting applications where OpenCL code might otherwise be used in GPUs for high-performance computing. Xilinx’s decision to put OpenCL into HLS seems to signal that they are going after the hardware designer – offering OpenCL as another option for hardware experts wanting a power tool for building hardware accelerators for performance-critical algorithms.
It is worth noting that the biggest benefit Vivado brings to Xilinx FPGAs is not in Vivado at all. For the new “Ultrascale” families of devices, Xilinx did exhaustive analysis of the routability of the chip architecture using Vivado. It’s a bit of a dirty little secret in FPGA Land that most FPGAs have historically had insufficient or inefficiently placed routing resources. As a result, we got big cell counts on our FPGAs that we couldn’t really use in real-world designs. As soon as we got to even modest utilizations – sometimes as low as 60-70%, there was a very real chance that our design would not be routable. With Ultrascale, Xilinx ran vast numbers of varying types of designs through the tools and placed-and-routed them on sample chip architectures. They iteratively re-designed the FPGAs themselves until they were consistently getting a very high utilization. This optimization of routing resources leads to FPGAs that we might think of as larger than they appear – because (for a change) we can utilize a very high percentage of the available resources.
Xilinx says they have improved runtimes, quality-of-results, and ability to use multi-CPU arrays with this release as well. With the size of some of the upcoming Ultrascale devices ranging into the millions of LUT4-equivalent cells, improvements in speed and QoR will be welcome indeed. In fact, when it comes down to the competitive game, it may well be the differences in tools that decide a winner, rather than the differences in chips. If that is the case, Xilinx is staging a strong entry in that tool race with Vivado.