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New MIPS CPUs are Virtually Better

M5100 and M5150 Add Tasty Virtualization to the MIPS Recipe

If multiple CPUs aren’t enough for you, how about multiple operating systems on one CPU? That’s what virtualization is all about, and MIPS now offers it in its low-end range of embedded microprocessor cores.

The CPU company that’s part of Imagination Technologies recently rolled out two sibling processors for embedded designers who have the budget for SoC development. The new M5100 and M5150 CPU cores add virtualization to the already familiar MIPS 32-bit architecture.

The M in the product name tells you that these are comparatively low-end MIPS processor designs, as opposed to the midrange I-series or the performance-oriented P-series. If you’re still stuck on the previously (short-lived) product names, this would be a microAptiv, not an interAptiv or proAptiv. Got all that?

The 51xx twins maintain all the usual MIPS goodness from previous generations, including the dual 32-bit and 16-bit instruction sets, DSP extensions, optional FPU, and room for coprocessors. Where the two designs differ is in their back-end interfaces to the rest of your chip. The 5100 is considered an “MCU design,” because it doesn’t have caches and has a somewhat more limited MMU. The 5150 sports dual caches, a “flash accelerator,” and a more fully realized MMU. (Public service announcement: 5150 is also the police code for ‘criminally insane.’ Just FYI.)

What the two cores share is an extra privilege level and related hardware to allow you to run up to seven(!) separate operating systems on one processor. You could always run multiple OS’s on a single MIPS CPU, but you had to tweak the OS code to do it. Now, the 51xx cores can host unmodified operating systems while still keeping them separate from one another. This kind of virtualization is getting more popular with embedded developers who want one OS for real-time control and another OS for the user interface or for backward compatibility. Virtualization can also enhance security by isolating code spaces from one another.

There are other security-related tweaks to the 51xx twins, but my favorite is the random-delay feature. With this enabled, the processor will insert random pipeline bubbles, or stalls, in order to thwart power-analysis hacks. And here I just thought my code was flaky.

The 5100 twins should run in the neighborhood of 500 MHz in 28nm silicon; expect 350-ish in a low-power 65nm process. As with most synthesizable CPUs, they can be optimized for either maximum speed or minimum area. Speed doesn’t kill, but it does cost you. A 5100 with all the goodies, including CPU, FPU, DSP, and dual 32K SRAMs will sprawl over 0.23mm2 of 28nm silicon when it’s optimized for speed. The same CPU core, minus the two SRAMs, occupies just 0.04mm2 of area with space optimization turned on, a more than 5× reduction. In 65nm silicon, the difference isn’t quite as stark (0.20mm2 versus 0.77mm2), since the SRAMs and the logic don’t scale the same way. Call me old-fashioned, but fitting a 32-bit MCU into just 0.04mm2 strikes me as pretty impressive. That’s a rounding error.

MIPS continues to keep pace with archrival ARM and the other CPU-licensing companies, producing new core variations as needed. The M51xx pair aren’t radically different from the entry-level MIPS cores that came before them, but their one big shiny new feature, virtualization, makes enough of a difference to keep potential customers on the phone. If embedded devices become as complex and security-critical as they seem to be, that virtualization is going to be an important feature. 

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