feature article
Subscribe Now

Smaller, Cheaper SerDes

Lattice ECP5 Proves Less is More

Over the past few years, Lattice Semiconductor has transformed itself from a struggling, distant third-place supplier of FPGAs to a scrappy, innovative competitor opening up new markets and challenging status-quo perceptions about the nature and role of programmable logic in system designs. Their latest press release proclaims they are “breaking the rules,” which would be easy to dismiss as marketing fluff, but it turns out those big ‘ol marketing boots are walking on some pretty solid footing in this case.

For years, we’ve talked about how FPGAs were trying to “replace ASICs.” In fact, ASIC replacement has been the battle cry of the FPGA companies for about as long as there have been FPGA companies. Every couple of years, with a new family based on a new process node, the FPGA companies come forth and say, “This time, we’ve done it. We’ve made an FPGA that can replace ASICs.”

Then, two more years go by, ASICs still exist, and the whole scenario plays over again.

The script goes like this: Design teams use FPGAs for prototyping and early production of some new system. Then, as that system goes mainstream, ASIC and ASSP implementations become available that reduce unit cost or power consumption, and those teams move to the ASIC-based solution. FPGA companies want to break that loop, of course, because they’d really like the big volume orders that come later – not just the comparatively small volumes from prototyping and early production. 

Two things work in favor of the FPGA companies, however. First, design teams have sometimes moved on to the next big thing using FPGAs before it comes time to cost-reduce the “old” thing using ASICs. (This doesn’t mean that ASIC-based cost reduction never happens, however.) Second, there is often some aspect of the programmability of the FPGA that is impossible to replace with an ASIC.

Lattice has an idea. Go right ahead and bring in that fancy ASSP or ASIC. Take the cost, power, and performance benefits it brings. Then, for the “programmability” aspect that you lost when you ditched that big, expensive FPGA – use one of the cool, cheap, remarkably capable ECP5 devices they just introduced. You’ll get all the benefits you were wanting from your big-iron FPGA solution – programmability, flexibility in changing standards, SerDes, bridging, and so forth – but you’ll also get to capitalize on the benefits of optimized ASSPs and ASICs.

It’s the best of both worlds, right?

ECP5 is, as you might guess from the name, (approximately) the fifth generation of Lattice’s popular low-cost (although the company calls them “mid-range”) FPGA family. The company says ECP5 is targeting applications such as small-cells, microservers, industrial video, or anything where high-volume production makes conventional FPGAs impractical. The common theme in these applications is a need for high-speed SerDes and flexibility/programmability. You can go full steam with your ASIC or ASSP solution, secure in the knowledge that the FPGA will clean up the loose ends that were missing in your ASIC, bridge any interfaces that don’t match up, and drive your high-speed serial data pipes. It’s a reasonable approach to getting your system out the door with minimal risk and in minimal time.

Lattice says the new family makes significant gains over the previous generation – 40% lower cost, 30% lower power consumption, and 2x “functional density” (amount of logic packed into the smallest package). ECP5 weighs in in the “less than 100K LUTs” category, which still leaves you a lot of logic in your sandbox. Interestingly, the company chose not to go “bigger” with this generation – keeping the density in the 25K – 85K LUT range, and focusing instead on delivering that amount of logic in smaller packages with lower cost and less power consumption. 

Of particular interest are the extremely low power claims for SerDes interfaces – “starting at 0.25W.” The 0.25W is for X1 PCIe, and x4 PCIe comes in at “

Speaking of target applications, Lattice seems to have had some specific ones in mind when they designed ECP5. If you’re designing a small cell base station, for example, they think ECP5 should be sitting between your analog front-end and your ASIC/ASSPs, supporting things like CPRI, ORI, digital front-end (DFE) augmentation, and JESD207 or 204B. If you’re doing video, they want to connect you with your image sensor, help with your image signal processing, handle your Ethernet and H.254 encoding, and more. Because the company has been focusing on mobile designs, they’ve got you covered on mobile-based standards like MIPI CSI-2 if your image sensor speaks that language, as well as on many other popular standards.

The available 10mm x 10mm package is designed to squeeze into the cramped quarters of an 11mm PCB, which just happens to be what you’ll want if you’re doing small form-factor pluggable transceiver modules (SFPs). ECP5’s SerDes can handle the Ethernet connectivity for you, and you can have those 85K LUTs for whatever secret sauce your heart desires.

The small die size is achieved by low-cost copper pillar fine-pitch flip chip technology and some pragmatic decisions on how many pins are needed for targeted applications. Even though ECP5 is based on seemingly pre-historic 40nm CMOS technology, the 7mm x 6.6mm die size is plenty small to deliver the cost, form-factor, and power benefits without the treachery of some of the more cutting-edge processes (like the current 28nm used for many mainstream FPGAs).

One final way Lattice breaks the rules is in their product announcement scheduling. While most of us are used to FPGAs being announced months (and sometimes years) before they are actually available, ECP5 is available now. You can download the tools, get yourself a development board, and start rocking. Weird, huh? Maybe they really are breaking the rules.

8 thoughts on “Smaller, Cheaper SerDes”

  1. yeah …. could be wonderful, if they were off the shelf at major stocking distributors. Tried both Arrow and Digikey … part numbers don’t seem to match in the site search engines.

  2. @bfienberg

    Thanks Bruce … I was just taking Kevin at his word when he said “While most of us are used to FPGAs being announced months (and sometimes years) before they are actually available, ECP5 is available now.”

    Available for small shops like mine, doing quick turn designs, means we can design, prototype, test, release to production, purchase and ship inside a few weeks without supply risks for the client. IE the product is already stocked in distribution … not a hand full of samples, with general availability in distribution being months away.

    Samples are just that … samples to test with. Off the shelf availablity from multiple stocking distributors is being actually available to design/ship with today, rather than a year from now with early availability samples.

  3. Pingback: 슈어맨
  4. Pingback: DMPK Services
  5. Pingback: go to my blog

Leave a Reply

featured blogs
May 18, 2021
Since I was a kid, I’ve always been a fan of technology making life better. When I was 8, I remember programming the VCR to record the morning cartoons so I wouldn’t miss the good ones after the bus picked me up from school. When I was 10, I made mixtapes of my fa...
May 18, 2021
原文出è•: Please Excuse the Mesh: CFD and Pointwise ä½è…: Paul McLellan Cadence於今年四æˆæ”¶è³¼äº†æµé«”動力學公司Pointwiseã‚å¨æˆ‘的前ä¸ç¯‡æ–‡ç« æŽ¢è¨Ž PointwiseãPCIeã...
May 13, 2021
Our new IC design tool, PrimeSim Continuum, enables the next generation of hyper-convergent IC designs. Learn more from eeNews, Electronic Design & EE Times. The post Synopsys Makes Headlines with PrimeSim Continuum, an Innovative Circuit Simulation Solution appeared fi...
May 13, 2021
By Calibre Design Staff Prior to the availability of extreme ultraviolet (EUV) lithography, multi-patterning provided… The post A SAMPle of what you need to know about SAMP technology appeared first on Design with Calibre....

featured video

Industry’s First USB4 Silicon Success

Sponsored by Synopsys

USB4 offers up to 40Gbps speeds for incredibly fast connections. Join Synopsys to see the first demonstration of USB4 IP in silicon, along with real TX eyes for DesignWare USB4, DisplayPort, and USB 3.x IP.

Click here for more information about DesignWare USB4 IP

featured paper

IP Solutions for a Data-Centric World

Sponsored by Cadence Design Systems

High-performance computing, data communications, networking, and storage systems are taking center stage in many application areas, driven by newer applications such as analytics, artificial intelligence (AI), genomics, and simulation-intensive workloads. Power efficiency, high performance, and small form factor are key requirements for such systems. This paper examines how Cadence’s pre-verified, standards-based design IP can help you deliver on your quality and time-to-market goals.

Click to read more

featured chalk talk

ROHM Gate Drivers

Sponsored by Mouser Electronics and ROHM Semiconductor

Today’s rapid growth of power and motor control applications demands a fresh look at gate driver technology. Recent advances in gate drivers help designers hit new levels of efficiency and performance in their designs. In this episode of Chalk Talk, Amelia Dalton chats with Mitch Van Ochten of ROHM about the latest in isolated and non-isolated gate driver solutions.

Click here for more information about ROHM Semiconductor Automotive Gate Drivers