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Imagination Deploys a MIPS Warrior

New P5600 “Warrior” CPU to do Battle with Cortex-A15

In the never-ending battle of good versus evil, Coke versus Pepsi, NASCAR versus opera, and ARM versus MIPS, the MIPS brigade has fielded a new combatant. Behold, the P5600, the point of the spear in MIPS’s epic battle to dethrone the incumbent Cortex as king of the microprocessor-IP hill.

But first, there’s the name.

Remember the MIPS “Aptiv” line of processors? Forget about it. Now that MIPS is part of Imagination Technologies, their British marketing overseers have overhauled the branding. Henceforth, MIPS processor designs will be known as the M-class, I-class, or P-class. Get it? M.I.P? All they need now is an S-class (like Mercedes-Benz) and the clever punning will be complete.

At least the sequence stays intact. The new P-class corresponds to the previous ProAptiv line of high-end cores; the midrange I-class matches up with the InterAptiv name, and the entry-level M-class corresponds to the old MicroAptive moniker. In short, Imagination is preserving the same old M-I-P progression but just ditching the –Aptiv suffix. I wonder how much that bit of market research cost.

Okay, back to work. The P5600 is MIPS’s top-of-the-line processor, which means the engineers have been at least as busy as the marketing department. As the company’s new flagship CPU, the P5600 competes directly with ARM’s Cortex-A15. Not the Cortex-A53 or –A57, you may wonder? No, because both the P5600 and the A15 are 32-bit cores, not 64-bit designs. So the P5600 sits at the top end of the lower range, if that makes any sense.

Not everybody needs a 64-bit CPU. For that matter, very few SoC designers do need a 64-bit CPU. Thirty-two bits ought to be enough for anyone, at least for a few more years, so the P5600 likely represents the fattest part of the revenue bell curve for Imagination’s processor product line. Neither too expensive nor too wimpy.

On technical merit, the P5600 gets the full five-star rating. It’s an impressive machine, with superscalar out-of-order execution, multiple dispatch, 128-bit data paths, specialized execution units, and a 16-stage pipeline that’s longer than a Russian historical novel. It gets the full SIMD treatment and handles both single- and double-precision floating-point numbers with ease. The only things it doesn’t have are support for threading and a 64-bit architecture. Both will likely show up later on the P5600’s successor.

Imagination puts a lot of emphasis on the P5600’s load/store bonding feature. This is an implementation-level technique that sniffs out consecutive load or store operations to contiguous addresses and combines them into a single bus transaction. This saves a bit of time on the bus, as you might expect, but it also makes the CPU’s caches and TLBs a bit more efficient. It’s the little things that add up.

Since MIPS and its archrival ARM are both nominally RISC architectures, there’s not a lot to separate them in terms of instruction set or mnemonic repertoire. Most programmers don’t care, anyway. Frankly, if it’s not supported by the C compiler, it might as well not be in the chip. Imagination feels that its instruction set has the edge here, hewing more closely to the RISC credo of implementing only instructions that the C compiler will use. The inference is that ARM includes too many “compiler invisible” instructions, implying a kind of impious impurity, a dangerous deviance from RISC ideology. But, as the lingering example of the x86 shows, you can never have too many instructions. Unless a new instruction slows down the entire pipeline, there’s no harm in implementing it. What’s a few million extra transistors? Maybe some enterprising assembly-language programmer will use the new opcodes, or some compiler writer will see fit to implement them. Simplicity, per se, is of no value to a programmer.

But it does have hardware benefits. The nip-and-tuck job makes P5600 smaller than its counterpart from Cambridge. About 40% smaller than a Cortex-A15, according to Imagination. That’s quite a trim for a CPU with about the same performance. Put a handful of P5600 CPUs into a four-core cluster (as designers likely will do) and you get something that’s about 30% smaller than ARM’s four-way A15 cluster. (Caches, buses, and other non-CPU logic are about the same size for both architectures, which explains the difference in relative area.)

For all its space efficiency, the P5600 handily outperforms its immediate predecessor. At the same frequency, a simulated P5600 is at least 20% faster than ProAptive, and in some cases twice as fast. In real silicon, the P5600 should consume about the same amount of power as ProAptiv, even in the same process technology. In 28nm silicon, the P5600 should easily hit 2 GHz.

All in all, the P5600 is a terrific piece of microprocessor engineering. It delivers more with less, all while maintaining binary compatibility with the dozens of MIPS-based CPU cores that came before it. It’s a necessary range-topper to help MIPS beat back the rising tide of ARM homogeneity. Look upon its work, ye mighty, and rejoice. 

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