There are two “go-to” products in the mechanical world – duct tape and WD-40. WD-40 for things that are stuck together and are not supposed to be, and duct tape for things that are not stuck together, but we want them to be.
The digital world has its duct tape too, of course. When you have two parts of your design that aren’t designed to talk to each other, you need some nice, sticky gates in between that will allow tab A to fit slot B, and not in a parallel-peg-in-a-serial-hole kinda’ way. In the old days, this was the job of “complex programmable logic devices” (CPLDs). Now, of course, CPLDs have pretty much gone the way of the dodo, and even devices formerly known as CPLDs are now made with LUTs – a decidedly FPGA-like feature.
But, no matter what you call it, the bridging device is a critical tool in any system designer’s toolbox. With the plethora of IO standards we are using today, the chances of needing to connect two incompatible components together in any given system design are approximately 100%. What we usually want in that situation is a device we can stick in between that is: A) Cheap B) Inexpensive C) Simple to design in D) low-cost E) low-power F) Did we cover the cost thing already?
Lattice Semiconductor has carved a nice spot for themselves in the FPGA and programmable logic market. Rather than going head-to-head with the rather dominant Xilinx and Altera in the race for the biggest, fastest, most expensive programmable devices on the planet, Lattice has staked a claim on all the territory below – where cost, power, and form factor are at a premium, and where production volumes are in the millions rather than the thousands. In this space, the company has shipped over a billion devices in the past decade. That’s lots of LUTs, folks.
Lattice proudly proclaims themselves the champions of the “Low-Density” and “Ultra-Low Density” FPGA markets – labels that might be considered insults in the parlance of other FPGA companies. With their acquisition of SiliconBlue, the company now even boasts the “World’s Smallest” FPGA, a headline that turns heads but might leave some scratching them as well. The people who aren’t scratching their heads, however, are the ones who need tiny, ultra-low-cost, ultra-low-power programmable devices for high-volume designs. They get the message – loud and clear.
Now, in the slightly higher density range, Lattice has announced their latest version of digital duct tape – MachXO3. Those familiar with the company’s Mach lines from the past will recognize the attributes of a classic CPLD – instant-on, low-cost, small footprint, non-volatile, and low power. The difference this time is that the job is much harder than in the past. We need our bridging devices to bridge much faster and more complex standards than in the past – and MachXO3 has been designed to answer that challenge.
MachXO3 offers a much higher IO density (up to 540 IOs) at a very low cost-per-IO (the company claims 1 cent per IO). In a nod to modern interface requirements, MachXO3 includes integrated MIPI, PCIe, and GbE. See? This is not your old-school CPLD. To help us fit all those IOs on a reasonable amount of board space, the devices are available in packaging with 0.4mm pitch (you can apologize to your board designers in advance), and even wafer-level chip scale packaging (WLCSP). Static power is in the micro-watts, and active power is in the milli-watts.
Lattice is targeting application areas like displays – where legacy and emerging standards crunch inconveniently into a wide array of display technologies, sizes, and resolutions. Want to get from a MIPI-compliant host to a legacy display? Or, what about the other way ‘round? You can use MachXO3 to go both ways. And, Lattice claims, it can do both tasks with significantly lower power and in smaller form factors than alternative processor-based or ASSP solutions. This is the kind of application where programmability shines.
The company is also going after sensor fusion applications – such as automotive driver assistance – where inputs from multiple sensors need to be aggregated. The company supports an automotive-grade version of the device – AEC-Q grade 2, so you car guys can go right ahead and start designing them in. Lattice even points out that the little XO3s would be an attractive part of a wired-comm board, if what you were after was a hot-swappable device that could connect to a backplane and standards like PCIe and GbE. The company points out that MachXO3 is the first “instant-on” FPGA with SerDes transceivers.
With a healthy set of interesting attributes, the little MachXO3 is likely to show up in a wide variety of applications – and in substantial volumes. While it won’t be setting the FPGA world on fire with the biggest or fastest anything, it will often be the best, most cost-effective solution for a wide range of design problems. And that seems to be the theme at Lattice these days. The company has found a bit of a new lease on life with a major cultural makeover, and with the realization that a lot more money can be earned by focusing on the needs of a large, underserved market than by butting heads with larger competitors on more glamorous devices. That’s why Toyota sells a lot more cars than Ferrari, even if their products are a bit more pedestrian.
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Lattice Semiconductor has done a major turnaround by focusing on the low-density and ultra-low-density FPGA/PLD market. Now, they’ve introduced a peppy new bridging PLD. Are low-density programmable devices making a major comeback?