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Systems on Interposer

“Chips” are So Passé

The term “SoC” has been in use for about two decades now. Systems-on-Chip were a great idea, of course. Over the years, as we marched forward with Moore’s Law, steadily reducing the number of chips in our systems, we could see the finish line ahead of us somewhere. Eventually, we reasoned, this increased integration would allow us to put our entire system on a single chip. Sure enough, for many of us, our design elements dwindled from dozens to single digits, and ultimately approached that magical vanishing point – unity – one chip to rule them all.

Eventually, we rationalized victory. The marketers amongst us were all too excited to be the first to proclaim, “We are doing System on Chip!” Banners were waved and bandwagons opened their admission gates. We were no longer simply Chip designers, we were SoC designers! Strike up the band! The future is here! We are now in the SoC business! 

Of course, we all knew we were really doing “SoC” design only for a sufficiently narrow definition of “System.” And that definition was narrow indeed – embarrassingly narrow, in fact. However with adequate peer pressure combined with a fear of being “behind,” we managed to allow ourselves the luxury of the label. If those “other” guys were designing SoCs, then what we were creating must also be. 

But what is a “system” anyway?

Ah, this is a tired question. It is the engineering version of the art-school “what is art?” debate. A colleague of mine once said, “A system is the thing one level of abstraction higher than what you can understand.” Personally, I like his definition. But, for most of us, a “system” is the thing we box up and sell to our customers. I doubt many of us ship simply a “chip” (semiconductor company employees get a pass on this claim, however). We have a lot of “other” things in our systems besides our SoC – RAM, NVM, sensors, power, analog, RF… all technologies that – while realized in silicon, don’t share a single process and therefore are excluded from our SoC – which, if we really have to admit it – is really just a computing subsystem on a chip.

The dawn of the 2.5D packaging era, however, has offered us a chance to come clean. Or, at least, to come “cleaner.” As we documented here, Xilinx was perhaps the first company to market a true 2.5D packaged device – CMOS chips connected through a silicon interposer. Xilinx’s first 2.5D offering was a conservative attempt – homogeneous FPGA slices cross-connected through an interposer to create, effectively, a larger FPGA device. While that was cool, and it proved that 2.5D packaging could actually be used in production, the real payoff for 2.5D packaging is heterogeneous devices – combining chips made with different base semiconductor processes on an interposer and packaging them as a single “device.”

Heterogeneous 2.5D interposer-based packaging gives us the opportunity to come much closer to our goal of “system on chip” (or in this case, system-on-interposer). We can fabricate each part of our system with the semiconductor technology best suited to that task – high-speed logic, low-power logic, memory, non-volatile memory, analog, power, MEMS, RF – each of these is best realized with different processes at the semiconductor level, and all of these could be combined into “systems” using silicon interposers. Certainly there would still be parts of our system that could not fit in this package, but we’d be closer than we are today by miles. 

Of course, we don’t want to do integration simply for its own sake, and that brings up the question – why? Combining chips on an interposer offers distinct advantages over packaging them separately and soldering them onto a PCB. First, the number of connections that can reasonably be supported between devices is much higher on an interposer than on a PCB. Basically, that means each chip or slice on our interposer could have considerably more “pins” than we can achieve bringing all those signals out through a conventional package. Second, since we don’t have to charge up those long PCB traces, it takes far less power (and time) to get a signal from one chip to another. So – speed and aggregate bandwidth go up, power goes down. Now we’re talkin’! Of course, form factor is improved too – cramming all those chiplets onto a silicon interposer means less suburban sprawl on our PCBs. As Bob Conn pointed out in his article “The Condensed Guide to Silicon Circuit Boards”, there are other benefits as well, including higher reliability and improved thermal performance.

But – there are some serious obstacles between us and 2.5D Nirvana. Today’s board-level ecosystem is robust, and it is centered around the notion that packaged ICs are the basic atomic currency. Few chip vendors offer bare die versions of their products, and there is little help available for the “little guy” wanting to assemble a system on a silicon interposer. At first, our Systems-on-Interposers are likely to come from fabless chip vendors like Xilinx, and from traditional SoC suppliers like Freescale, NXP, and others. We might also expect ASSP companies like Broadcom or Qualcomm to more broadly adopt 2.5D technology. These “big fish” jumping into the pond should help to flesh out the ecosystem for the rest of the market.

It would also be helpful if there were some standards for inter-chip interconnect via interposer. Today, you’re pretty much faced with a full-custom interposer design for whatever combination of devices you want to use. If you substitute in a different device – or even a similar device from a different supplier, all bets are off. You’re likely in for a major re-design.

One question that remains is who will be the system integrators for systems-on-interposer. If the “big fish” are truly the semiconductor companies like those we mention above, we might expect both “general purpose” systems-on-interposer and “application specific” ones. Xilinx, Altera, Freescale, NXP, TI and the like might be expected to produce systems a logical step beyond their general-purpose SoCs of today – with the integration of additional peripherals such as memory, MEMS, analog, RF, and so forth. ASSP companies might similarly get closer to the idealized version of what they’ve been selling in their SoC offerings – the “phone on a chip” or “router on a chip” could be much more complete on an interposer-based implementation. 

There also seems to be a possible play for integration houses – in a similar vein to the old “ASIC Vendor” model. Integration houses would have expertise and IP for creating systems-on-interposer, and they would provide services to systems companies wanting to create custom solutions using the technology. Perhaps such integration houses could bridge the gap between the system-level needs for integration and the specialized capabilities required to create a 2.5D chip. 

However it plays out, 2.5D technology promises to substantially change the nature of system-level design over the coming years. It will be fun to watch!

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