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The Bell for Round Two

Xilinx Upgrades Vivado

The big battle in FPGAs has traditionally been fought at the chip level. For years, we have endured press release skirmishes over who had 20% lower power or 10% more LUTs on their devices. FPGA companies’ boom and bust years hinged largely on who got to market first with next-process-node silicon. This Moore’s Law arms race has escalated for over two decades, with staggering costs. Today, if you don’t have a 9-figure sum to invest, you’re not going to have FPGAs on the next process node.

In parallel to the silicon race, however, another war has raged – albeit less visibly. This quiet competition is more likely to determine business success over the coming years than silicon. This battle is over design tools. 

The history of the design tool competition in FPGA is long and storied. The EDA industry has played an important role, which we have discussed many times, but Xilinx and Altera have certainly shouldered most of the weight and controversy in FPGA design tools development. Last year, we explained how Xilinx took a dramatic wingsuit dive off an engineering cliff when they announced a ground-up redesign of their aging tool suite – releasing a completely new integrated solution called “Vivado”.

Everyone (and this probably even includes Xilinx) expected Vivado to be somewhat of a catastrophe – at least in the early going. One does not spend years writing millions of lines of fresh, unproven code and unleash it onto an unsuspecting public without accepting the near certainty that there will be critical bugs, major oversights, some unhappy customers, and some serious support issues. This is to be expected even if you have the best software development team in the world. The key is how you respond to that self-induced state of trauma. If you are nimble on fixing critical bugs, listen closely to customers, and give outstanding customer support, you eventually get past the initial wave of confusion and settle into the benefits of a new, shiny software product.

Xilinx seems to have done fairly well on this front. They did a very measured release of Vivado – starting with close, trusted customers and gradually broadening the audience, controlling the scope of the exposure so their support resources were not overwhelmed. Now, Vivado is in general release and the company has just announced the first major upgrade, Vivado 2013.1, and the content is interesting. Xilinx is taking the fight to the system level and providing tools to accelerate IP-based design.

The feature attraction in Vivado 2013.1 is definitely the new IP Integrator. Xilinx says that the IP Integrator is “a new graphical and TCL based, correct-by-construction, IP- and system-centric design development flow.” That description really doesn’t do it justice. We’ve all seen a lot of these “system level” design tools through the years. Usually, these types of tools are nothing more than glorified schematic capture – allowing the user to stitch together IP blocks into a top-level design, then generating the HDL hierarchy. These flows generally break down pretty badly when one tries to use them for real work. The reasons for failure range from the complexity of connecting real-world blocks correctly to getting the required IP into the system in the first place, to a host of other gnarly pitfalls waiting to frustrate the hopeful HDL-avoider trying to get an FPGA design done. 

IP Integrator is much better than that.

The secret to getting one of these system-level IP-block-based design tools to be useful for real work is in the details, of course. Xilinx seems to have covered the bases nicely on the usual failure mechanisms. First, they’ve made what seems like a major switch in their attitude toward standards. In this case, the tool is driven by IP packaged with the IP-XACT, which is a standard from the SPIRIT Consortium for XML data to accompany IP blocks. IP Integrator is able to take advantage of this to provide a huge library of compatible IP right out of the chute. This is normally one of the first failure points for system-level design tools.

Another detail that often trips up system-level tool users is the disconnect between the top-level design and the detailed implementation. With most tools, if the user makes mistakes at the top level, they don’t find out about them until much later – in steps like synthesis, place-and-route, or simulation. By that time, the design is at a completely different level of detail, and it can be extremely difficult to trace the error back to the fault on the original block diagram.

IP Integrator solves this problem primarily in two ways. First, it shares a common, completely integrated database with the rest of the Vivado flow. As a result, cross-probing is available from the highest-level block diagram down to the most detailed LUT-level description. If your bug manifests itself at the lowest level, it’s easy to traverse back up the layers of abstraction and levels of hierarchy to see where that error occurs in the design description you actually created – not in some detailed netlist populated with auto-generated instance names for things you never knew were part of your design in the first place.

Second, IP Integrator works to make sure you never create the error in the first place. It brings a robust set of design rule checks to bear while you are connecting up your design, and it helps you complete that process by intelligently making those connections for you. You connect IP blocks at the bundle level in IP Integrator, and it understands the various types of connections that need to be made. It also understands what cannot be connected, and it will remind you when you forget to connect everything required to get a block working properly. IP Integrator understands the interfaces to IP blocks at a much more useful level than simple matching of signals and busses. It has a great deal of context-specific understanding of things like clock domains and data types, and it will warn you if you try to make a connection that doesn’t make logical sense for a particular block. As a result, by the time you’ve got your IP-based design assembled in IP Integrator, the number of hidden bugs that are waiting to bite you down the road is dramatically reduced.

IP integrator has the potential to actually deliver on the promise that “system-level” design tools have been making for years – making IP-based design re-use a normal part of the FPGA design flow, and either drastically reducing, or in some cases completely eliminating the need for original HDL coding. If it succeeds at that, it will have opened the door to FPGA implementation for a broader class of engineers who don’t have specific expertise in HDL and the associated design tools.

There are other goodies in 2013.1 as well – Xilinx now supports Zynq devices with Vivado – previously Vivado supported only the 7-series FPGAs. The company has also made major enhancements to their high-level synthesis (HLS) capability – including much larger and more robust libraries – to improve the usefulness of the HLS flow for accelerating key algorithms in hardware FPGA fabric.

Vivado is a big change from ISE – Xilinx’s legacy tool suite. There is a learning curve – particularly in areas such as expressing timing constraints in industry-standard SDC (rather than the proprietary Xilinx format that many customers are used to). While moving to an industry standard is good, any change is disruptive. Xilinx says that users coming up to speed on SDC has been one of the big support sinks for designers transitioning to Vivado.

Xilinx says adoption of Vivado has been brisk – with approximately 50% of 7-series designs being created with the new tools. The company says adoption of HLS methodologies has also been surprisingly broad – with over 350 active customers and over 1,000 active evaluations of HLS for FPGA design. These numbers would probably make Xilinx the #1 supplier of HLS tools, but the EDA industry analysts who count tool penetration don’t look at FPGA vendors like Xilinx as EDA companies – despite the fact that Xilinx and Altera each have enormous design tool groups and supply and support perhaps more customer design tool installations than some of the large EDA companies.

Xilinx claims that the improvements in Vivado can result in a 4x improvement in design time. Numbers like this are always suspicious, of course. But, specific numbers aside, if a company could create a design tool environment that would reliably accelerate the time, reduce the effort, and most importantly facilitate the expertise required to get an FPGA design up and working by a significant factor, that advantage would translate into a serious market advantage. Such an advantage would probably be more important than even a significant difference in silicon performance, cost, or power consumption. If you could get your design up and working correctly four times faster, you might care a lot less about a 15% difference in speed or 20% in power. 

At some point, Moore’s Law will probably come to an economic end. Then, semiconductor companies will have to differentiate themselves on other aspects of their products and services. In the programmable logic arena, tools are at the top of that list.

13 thoughts on “The Bell for Round Two”

  1. The IP Integrator feature is early access in 2013.1 but it is shipped as part of every copy of Vivado 2013.1. Customers just need to ask their local FAE for a license to enable it.

  2. There was a bit of confusion caused by a post on John Cooley’s site reporting (incorrectly) that Atrenta’s SpyGlass was included as part of Vivado:


    We wanted to clear this up, so we checked with Mike Gianfagna, Atrenta’s Vice President of Marketing to clarify. Gianfagna told us:

    “The Vivado flow, including the interface hooks to SpyGlass, is available from Xilinx. The actual software required to complete that part of the flow is available from Atrenta. This is a common practice for third-party interfaces – the interface is available from the initial provider, but the software needed to complete the interface is available from the third party. This way everyone supports what they sell.”

    Thanks to Mike for helping eliminate the confusion.


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