The FPGA market is, in many ways, a microcosm of the explosive and volatile semiconductor industry. FPGAs leapt to the front of the line in new process technologies about a decade ago – assuming the role of canaries in the Moore’s Law mines. Every time the semiconductor industry managed to reach a new technological milestone, FPGA companies raced to get the first devices to market – in order to capitalize on the bounty of the new node.
Unlike other semiconductor devices – processors, memory, etc. – FPGAs are in a unique position to take maximum advantage of Moore’s Law improvements in semiconductor technology. FPGA companies turn this technology advantage into market advantages – and into some of the biggest margins in the world of semiconductors. Each new process node brings a bounty to the world of FPGAs – usually in the form of lower power consumption, greater density (and thus greater functionality), larger IO capacity and bandwidth, and – to a lesser degree, more speed.
Fundamentally fueling the FPGA rocket… are dogs skateboarding. That may sound a bit strange. With the number of smartphones on Earth exploding – and reaching a number equal to a sizeable percentage of the world’s population, and, with a significant portion of those people wanting to do high-bandwidth tasks on those smartphones (and tablets, and other “connected” devices) – such as watching videos, we have a global appetite for bandwidth that is almost incomprehensible. With the growing popularity of cloud-based services, there is no sign of that voracious appetite waning anytime soon.
The people in the business of building the pipes that carry all that data – the Ciscos of the world and their kin – are by far the largest users of FPGAs. Anything the FPGA companies can do to let them build bigger data pipes and switches is warmly welcomed. Anything the FPGA companies can do to reduce the power consumption and cost of those data pipes is an enormous bonus. While FPGA companies have been working diligently to expand FPGAs into other markets – consumer, automotive, industrial, display, etc. – the biggest line on the revenue sheet is still communications and networking.
As we mentioned in our recent article on the new Achronix/Intel FPGA collaboration, the high-end of the FPGA market has been a stable duopoly for years. Xilinx and Altera play the one-two roles almost as poster-children for a duopoly marketing textbook.
Now, the stability of the high-end FPGA duopoly is being challenged.
First, a couple of years ago, Xilinx and Altera chose the same semiconductor fab (TSMC) for their 28nm families. There is still some process divergence however, because Xilinx and Altera chose different variants of the 28nm process, which had important strategic implications for the two companies. On 28nm so far, the technological edge probably goes to Xilinx. They got more devices to market faster, with more differentiated capabilities, and they may well have captured back some recently-lost market share from Altera. It’s too early to know this for sure, however. Today’s market share numbers are based on older devices whose designs have gotten into big production volumes. Design-ins of 28nm FPGAs haven’t had a chance yet to account for much revenue impact. That will show up in the financial results in a couple of years, when more of today’s 28nm FPGA-based designs are in higher volume production.
Moving ahead from 28nm, though, the situation just got a whole lot more interesting.
First, as we discussed last week, two newer companies – Achronix and Tabula – have been collaborating (separately) with Intel for the past couple of years. This is important for several reasons. First, Intel has never operated any significant business as a merchant fab company. Second, they have never (to our knowledge) let external companies have access to their latest/greatest process technology. Third, that latest/greatest process technology has long been believed to be two to four years ahead of all other semiconductor companies – or, in Moore’s Law terms, a lead of one to two process nodes.
In the hands of a competent FPGA company, a two-process-node lead could be deadly.
However, there is reason for some comfort there amongst the big two FPGA players. As Altera CEO John Daane explained when we chatted with him last week, “There have been no successful FPGA startups in the past twenty years.” So, even though Achronix and Tabula running amok with a two-process node advantage may seem terrifying at first, the big two FPGA companies have formidable fortifications – in the way of highly-evolved tools, large customer bases, well-trained AE armies, established market reputations, and volumes of IP.
But, Achronix and Tabula have gotten farther, with more pointed attacks, than any of the attempts of the past two decades. They both have sold previous-generation families with some degree of success. They both have apparently-workable tool flows supporting their devices. Now, they both apparently enjoy what might be a two-process-node advantage over Xilinx and Altera. And, they both are apparently going after the golden goose of FPGA – the communications and networking infrastructure market.
This means the traditional two-horse race has a very real chance of becoming a four-horse race, which, as any economist/market strategist will tell you, has a completely different dynamic than a stable duopoly. Defending against an expected attack from a well-known attacker – from one direction at a time – is a wholly different task than defending against multiple, independent, simultaneous attackers with diverse strategies and capabilities. To put it another way – the entrance of Achronix and the expected entrance of Tabula just made the FPGA Wars a whole lot more exciting.
Last week, Altera’s announcement that they will be cooperating with Intel to develop and manufacture FPGAs based on Intel’s 14nm Tri-Gate process – took that “more exciting” and cranked it up to 11. By joining forces with Intel, Altera puts themselves on a 2- to 4-year track of process parity with the two new interlopers (Achronix and Tabula). That’s an important defensive move. Further, according to John Daane, Altera’s agreement with Intel means that no other “major FPGA company” (which means “not Xilinx,” if your CEO-speak subtitles weren’t working) will be working with Intel on 14nm.
At about 20nm, we expect planar CMOS to pretty much run out of gas. The advantages of 3D “FinFET” (or as Intel calls theirs – “Tri-Gate”) technologies are substantial. For purposes of FPGAs, it’s probably fair to say that FinFETs give an additional process-node worth of advantages over planar CMOS at the same size. So – 20nm planar CMOS is more like 2 nodes behind 14nm FinFET. Both Xilinx and Altera have announced that they are working with TSMC on 20nm planar CMOS FPGA families. Those families are not expected (by us) until around the end of 2014.
Now, with Altera’s Intel/14nm announcement, Daane tells us that Altera is still proceeding with 20nm TSMC. After that, though, our crystal ball says that Altera, Tabula, and Achronix (assuming the two new attackers survive the first melee) will all be producing high-end 14nm FPGAs with Intel (and each with dramatically different architectures). Xilinx’s plans remain officially unknown, but they are assumed and rumored to be working with TSMC on FinFET-based FPGAs – which we presume to be TSMC’s upcoming 16nm process. If that’s true, Xilinx may be at a disadvantage, as we expect Intel’s 14nm Tri-Gate to be both superior (for FPGA use) and sooner to volume production than TSMC’s 16nm FinFET.
On Xilinx’s side are a long-standing reputation as #1 in FPGAs, a recently completely-revamped tool suite that is reported to be the most sophisticated on the market, a wealth of IP and partnerships to leverage, and strong customer relationships and loyalty. Will that be enough to carry the company through a period of disadvantage on semiconductor technology? Does Xilinx have other irons in the fire that we don’t know about (like collaboration with Common Platform members such as IBM, Samsung, or GLOBALFOUNDRIES)?
Will Altera’s partnership with Intel be their ticket to finally slide to the #1 spot in FPGAs? Moving from #2 to #1 in a long-standing duopoly is an almost unheard-of feat, but there are reasons to believe it’s possible in this situation. Will Altera’s Quartus II tools have the longevity to keep them competitive with Xilinx as the technology explodes into these new, challenging process geometries? Will Altera be able to mount a meaningful attack on their long-time rivals, while simultaneously holding off well-funded and determined insurgents like Achronix and Tabula?
Will Achronix have the funds and fuel to follow through on their vision – to capitalize on the process advantage of their early partnership with Intel, and to keep their focus on the key revenue markets of FPGA? Will the rest of their battleship (tools, services, and IP) be up to the challenge of really competing with the big-two vendors?
What will Tabula’s anticipated announcement bring to the party? All we know officially so far is that the company has been working with Intel for at least a couple of years on FPGAs – presumably with the company’s radical “spacetime” time-multiplexed architecture. If they’re on a similar track to production with Intel as Achronix, we can guess we should be hearing from them soon as well. That may bring even more intrigue to this already-boiling cauldron.
Grab your popcorn – this is gonna be fun!