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Ahead by a Node


Let’s just get one thing out of the way before we talk about GLOBALFOUNDRIES’ new 14XM process. In electronics, almost nothing is actually what it is named. That’s because names are generally created by marketers rather than engineers. This is actually a good thing. Engineers are way too honest and specific. If engineers named solar panels, instead of “200W Solar Panel” we’d have “Photovoltaic Panel With Somewhere Between 0W and 140W Output That Could, Theoretically, On A Perfect (and Cold) Day At The Equator, With Some Cloud Edge Boost, Within the First Six Months of Deployment, With a Perfectly Clean Glass, Produce Close to 196W Output” 

See? Engineering-generated titles don’t just roll off the tongue.

As much as we’ve covered the FPGA industry, we live with this phenomenon every day. For example, how many LUTs in a 75K FPGA? Ah the easy answer would be 71,642 (which is admittedly a big ‘ol “marketing round-up” from 75K. However, the 71,642 number is not the number of LUTs actually on the device. It’s an estimate of the number of 4-input LUTs that would be required to realize the same amount of logic as the actual, physical, wider LUTs that are on the FPGA.  How many of those actual physical logic cells would we find on a “75K Logic Cell” FPGA? How about 44,776? Welcome to the wonderful world of Marketing nomenclature.

So, when GLOBALFOUNDRIES told us about their new “14nm” FinFET process, we had our marketing-proof goggles fully activated. With everybody we know currently struggling at the “bleeding edge” of 22nm FinFET or 20nm planar processes, we were skeptical at best that anyone had a 14nm line ready to engage. To be fair to our marketing friends out there (if we have any left), semiconductor nodes haven’t been named with any kind of rigor for a couple of decades. While the node number used to refer to a specific dimension like the channel width or the half-pitch or some other cleanly-measurable feature size, the blurry mess we get with today’s lithography techniques really doesn’t lend itself to any such specific measurement. Throw 3D features like FINFets into the mix, and you end up with a truly unmeasurable quantity. It’s like calling your vintage Porsche a “14-foot” car. The metric is less than useful. 

Instead, what most really do today is to try to quantify the benefits of the new process node relative to the last one in terms of “PPC” (Power, Performance, and Cost.) We know what the next node number should be by doing simple math on Moore’s Law, and we know what the usual gains are in the PPC space for a process node. If we are fabricating something with features roughly the right size, and we’re getting about the right total improvement in the key metrics, we’re happy to call our new process the expected name. 

How does this relate to GLOBALFOUNDRIES 14XM? Well, we wanted to get to the bottom of that, so we talked to an actual engineer – Subi Kengeri, VP of Advanced Technology Architecture at GLOBALFOUNDRIES. Subi explained that the past few years have seen a shift toward mobile devices as the primary process drivers for semiconductors. In mobile, as we all know, power consumption is king. Sure, we need spectacular levels of performance, and consumers have grown accustomed to paying less than the price of a good restaurant meal for a supercomputer that fits in their pocket, but the thing has to last all day on a battery that will fit inside the case.

In previous process nodes, most foundries offered several “flavors” of their process – one optimized for raw performance (perhaps for the CPU guys), another optimized for low power consumption (maybe for the mobile crowd) and so forth. At the 20nm node, however, the cost of providing all those “flavors” got prohibitively high, the differentiation between those flavors got smaller, and the demand for wafers became dominated by the needs of the mobile market pumping out millions of smartphones – outfitting every man, woman, and child on the planet with a new one every two years. As a result, we should expect that 20nm and beyond will be one-flavor-fits-all, and that the needs of the mobile market will drive the tradeoffs at the process level.

Somewhere around the 20nm node, Subi explains, planar transistors start to run out of steam. We can make them still smaller, but the usual gains in PPC are just not there. There’s little point in continuing to make our process smaller and more expensive if the overall performance metrics don’t get significantly better, so something has to give. In this case, the thing that “gives” is the planar transistor itself. 3D transistors such as FinFETs or Intel’s “Tri-Gate” technology that wrap the gate around a fin-shaped source and drain bring much better power characteristics, less leakage, and more performance to the table. Since these 3D transistors have all kinds of new measurable dimensions, it’s hard to say just what size they really are. So, if one of these transistors has some of the dimensions one would expect from 14nm, and it performs and quacks like a 14nm transistor should, who’s to say it isn’t a duck? er 14nm transistor?

Life isn’t all transistors, though. When we jump from one process node to the next, all sorts of demons rise up to obstruct our progress. Many of these challenges result from aspects of the new design rules that aren’t transistor related. The other dimensions of the process shrink can wreak havoc on the design of our IP blocks, causing us significant engineering investment. According to Subi, these other effects would be particularly tricky at 14nm – which is why GLOBALFOUNDRIES has chosen to put their 14nm FinFET transistors into their existing 20nm process. All the design rules, routing, and other considerations are the same as their 20nm planar process, but the transistors are the new 14nm FinFETs – with all the power and performance benefits those bring to the table. This means we don’t get the density advantage we’d expect from 14nm, but the other metrics improve perhaps even more than we’d expect. The upside of this tradeoff is that the work we did getting our design to function correctly at 20nm translates directly to 14XM. As an added bonus, we get to use it at least a year earlier than any other 14nm process. Ready to start now? Go!

In addition to having overall better power/performance characteristics, the voltage/power curve is flatter for 14XM – meaning that Vdd can be lowered more with less loss of performance. Lower Vdd means lower power – the company claims that at higher Vdd, 14XM has about 20% better performance, scaling up to 55% better at lower Vdd values. The company estimates that this will yield 40-60% better battery life, depending on the application.

While more performance with less battery is the golden egg from the 14nm goose, Subi tells us there are other, less obvious benefits as well. The biggest of these is probably for analog designers. It seems the FinFET has considerably better analog characteristics (linearity, etc) than its planar brethren. With today’s mobile SoCs packing a good deal of analog functionality – everything from transceivers to DACs and ADCs – good analog performance and characteristics are becoming more and more important.

The bottom line here, marketing claims and magic numbers aside, is that GLOBALFOUNDRIES seems to have a process that delivers what we all expect from a 14nm process – but a year earlier and with less re-design headache. While the windfall of benefits clearly lands in the laps of mobile device designers, there is plenty of bounty left over for just about anybody who might be motivated to move to the next stop on Moore’s train.

One thought on “Ahead by a Node”

  1. GLOBALFOUNDRIES seems to have jumped a year or so ahead on the 14nm race. Are they cheating, or is this engineering pragmatism at its best? Would you see value in starting a design for this process?

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