Today’s FPGAs implement the equivalent of millions of ASIC gates and continue to grow in size and complexity. With the increasing amount of time designers are spending debugging and diagnosing the design, there is a need both for better ways to find errors early and en masse, and for smarter techniques to isolate errors and apply incremental fixes. The newest generation of the Synplify Premier synthesis tool addresses these needs by supporting early design checks and hierarchical design approaches.