The definition of what FPGA really means has changed dramatically over the last two decades. Whether blazing the trail or being on the trailing edge of Moore’s Law, this is an exciting time to be an FPGA Designer. New opportunities bring new challenges for the FPGA market. As devices grow and become more complex resembling complete systems, the task of verifying such a system becomes daunting.

Mentor Graphics can help. By providing the latest technology for improving debugging, providing coverage, and accelerating testbench development, we have the needed tools and expertise to get your products out the door faster and with higher quality. We have created a 3-part seminar series to help you get started with using assertions for debug, code coverage for providing coverage, and UVM Express for improving your testbenches and accelerating the development process. In addition, take a look at the OVL white paper which takes you step-by-step through how to use OVL to do assertions. There is also an article on assertions that is a companion piece to the white paper.

If that is not enough to get you going, we have an entire FPGA section on our wildly popular Verification Academy site. All the resources are at your fingertips to get you verification ready and to get ahead of your competition.

Click the link below to view “Injecting Automation into FPGA Verification On Demand Seminar Series“

Click the link below to download the whitepaper “FPGA Verification with Assertions, Why Bother?“

Click the link below to read Harry Foster’s latest article: “FPGA debugging with Assertions“