This 3-part series will help you get started with using assertions for debug, code coverage for providing coverage, and UVM Express for improving your testbenches and accelerating the development process. Stay ahead of your competition by deploying these verification techniques at your company.

Improved Debug with Assertions:

The first FPGA Verification session “improved debug with assertions” provides a strong case for a step by step method for the adoption of assertions. All the sessions discuss steps for incremental adoption of assertions into your pre-lab verification process. Who is using assertions? What assertion languages and libraries they are using and why assertions add value. We also recommend where to place assertions, and an overview of how to apply them.

Providing Coverage

The second FPGA Verification session “Providing Coverage” describes code and functional coverage, and how each of these verification techniques can be applied to your verification process.  Step by step adoption flows are presented.  Answer questions about how coverage can improve FPGA lab productivity. What is the benefit of adding functional coverage?. What is the impact of code coverage? How to deploy new processes and manage FPGA project demands.  Why does coverage matter and how to leverage FPGA verification process improvements.

Improved Testbenches

The third FPGA Verification session “Improved Testbenches” describes how you can leverage existing verification IP to significantly improve your test scenario generation, stimulus generation, and coverage visibility. A step by step process begins with a focus on how to build up transactions based on the functionality of your FPGA design’s interface(s), and reuse the designs functions described as transactions for adding random test generation and coverage collection.  Improved processes like these give you control and visibility of your pre-lab verification environment.