The benefits assertion-based verification (ABV) have been talked about for years. However, for many FPGA engineers with little time available to learn newer advanced functional verification techniques, assertions seem overly complex—and the method of creating them remains a mystery. This paper provides a practical, easy, step-by-step set of instructions on how to add assertions to your RTL design. By following the simple guidelines provided in this paper you will benefit by cutting simulation debugging time in half, as well as finding very complex bugs that are likely to escape traditional simulation without assertions.