It takes a lot of guts to go head to head with an established industry leader. It takes even more guts to go up against an established duopoly – directly in their most heavily fortified markets. Fighting against one giant is tricky. You have to look carefully to find a vulnerable spot and put all your energy into exploiting that vulnerability. Fighting against two different giants is a whole ‘nother ballgame. What works against one opponent may not work against the other – and giants tend to be big and heavy. You don’t want to get squished between them.
Achronix apparently has a lot of moxy, because they have just declared war on FPGA industry leaders Xilinx and Altera – directly in their respective wheelhouses. For years, the two big programmable logic market leaders have battled each other over market share points in the most lucrative segment of the FPGA space – communications and networking. In many of these applications, FPGAs are the only devices that can provide a satisfactory solution. Furthermore, these design teams tend to always need the biggest, baddest FPGAs that the industry can produce. No matter how fast your chips are – they want faster ones. No matter how much logic you can cram on a die – they want more. They’re always pushing the state of the art.
Furthermore, these customers tend to be less cost-sensitive than those in other markets, so margins for FPGAs that deliver the goods are traditionally, ahem, healthy. These factors combined mean that the two big FPGA companies have enjoyed a lot of years fighting over market share borders in a very lucrative pie.
This week, Achronix announced details of their new 22nm FPGA families based on Intel’s Tri-Gate 3D transistor technology. These devices are designed to compete directly for the golden eggs of programmable logic. This part of the announcement is not a surprise. We have known for months that Achronix was planning to build big, fast FPGAs based on Intel’s process. What we didn’t expect was that these FPGAs would be a more conventional design than the previous generation Achronix devices (which featured a pipelined asynchronous FPGA fabric). For all intents and purposes, the first new family of the two just announced by Achronix are conventional LUT-based FPGAs – with some solidly engineered features that should make communications, networking, and test customers take a serious look.
Achronix is announcing two distinct families of devices based on Intel’s process. The first (the Speedster22i HD family) is based on a conventional LUT architecture. The second, to be rolled out a few months later, (the Speedster22i HP family) is based on the picoPIPE pipelined asynchronous architecture for which Achronix has been known in the past. While the HP family is the more interesting in terms of engineering novelty, the HD family is the moreinteresting in what it represents in market strategy for the company.
Releasing a conventional-architecture high-end FPGA to compete directly with Xilinx and Altera for their most valued customers requires some serious differentiation. Achronix believes that they have this differentiation, primarily based on two factors: Intel’s lead in process technology and Achronix’s choice of hard IP blocks aimed specifically at the target market. The combination of these two factors make a compelling story and will certainly garner the attention of design teams trying to squeeze the most bandwidth out of FPGAs with the least power and lowest cost.
First, Intel’s 22nm Tri-Gate process is believed by many to be at least a generation (and perhaps more) ahead of the current best 28nm processes from merchant fabs like TSMC (who manufacture both Xilinx’s and Altera’s flagship FPGAs). The Intel Tri-Gate technology uses a stacked transistor architecture that effectively triples the gate area – providing more performance for less power. In FPGAs, process advantage is king – which is why the big two vendors go to such great lengths to race each other to the next process node. Normally, any interloper (like a new FPGA startup) faces an almost insurmountable disadvantage because they typically don’t have the resources or the access to match the process technology of the two big vendors. This may be the first time that a startup has had access to a process that may actually be ahead of the big two – and that fact may be making the big guys just a tad nervous.
Second, for years, the big FPGA companies have faced a challenge of expanding the market. While the telecommunications infrastructure segment has unquestionably been extremely lucrative and still forms the core of the revenue stream for these companies, shareholders need to see the potential for the kind of rapid growth that can come only from expanding into new markets. In technical terms, that means that FPGA companies needed to adapt their products to do a lot more than just networking applications. Over time, they’ve expanded the feature set to include capabilities and flexibility that allow big FPGAs to be useful in a wider variety of applications – opening up new possibilities for market expansion. However, these new features come at a cost, because those new features and flexibility don’t come for free. By building devices that are more general-purpose in nature, Xilinx and Altera necessarily had to make them slightly less optimal for their traditional core applications. Of course, as long as both of the big companies were doing it, there was no competitive disadvantage in practical terms. Parity was maintained. However, Achroinix is attempting to take advantage of that trend by focusing and optimizing their devices – and particularly the choice of hardened IP blocks – directly on those target core communications and networking applications.
Specifically, this “hardened IP” includes the entire I/O protocol stack for 10/40/100 Gigabit Ethernet, Interlaken, PCI Express gen1/2/3 and memory controllers for 2.133Gbps DDR3. The hardening of these functions accomplishes two things. First, it improves the performance and power consumption of critical areas of target applications. Second, it frees up significant amounts of LUT fabric that would normally be used for these functions in other FPGAs. That means you can get by with a smaller LUT count for the same target application, with correspondingly lower cost and power consumption. The company claims that the net benefit of these advantages could be half the cost and half the power of the same function on a competitive FPGA.
While it is obvious that the process advantages come from Intel, it turns out that the hardened IP portfolio and packaging technology benefits from Intel’s help as well. In addition to I/O and core IP, Intel supplies packaging technology that has allowed Achronix to offer a ginormous (not a real technical term) 52.5×52.5mm package with pin counts up to a shocking 2,597(with a conventional 1.0mm pin spacing). That provides up to sixteen 28-Gbps SerDes, sixty-four 12.75 Gpbs SerDes, and 960 general purpose IO. This brings a total aggregated bandwidth of approximately 4.5 Tbps. Additionally, Achronix SerDes are independently clocked – making them more usable in some cases than architectures that gang SerDes transceivers together in banks.
The HD family consists of four devices boasting densities from 244K to 1.6M equivalent 4-input LUTs. Block RAM ranges from 16,000 Kb to 138,240 Kb. While not heavy on DSP resources, the devices do include 110-864 28×28 multiplier/MAC units. The coming-slightly-later HP family includes two devices with 312K and 552K equivalent LUTs, 30,240-64,240 Kb block RAM, and 702-1,760 multipliers.
The HP family will also boast blazing fast clock speeds (up to 1.5 GHz, according to the company) based on the company’s proprietary picoPIPE architecture. As we have discussed before, picoPIPE inserts tiny pipeline stages between chained combinational elements – allowing the design to perform more like an asynchronous network. The result is the elimination of long-chain critical paths that typically cause timing closure nightmares and performance limitations in conventional FPGA designs. The company says the picoPIPE architecture is advantageous for “feed forward” dataflow and DSP applications.
One place where new FPGA companies typically stumble is in design tools. In this area, Achronix has already established a track record over the past few years. The new families use the third generation of the company’s “ACE” Design tool suite. With ACE, Achronix has partnered with established EDA companies like Synopsys and Mentor Graphics, along with internally-developed capabilities.
Achronix is already engaging with early access customers and plans to ship engineering samples of the first (and largest) member of the HD family – the HD1000 – in Q3 2012. The remaining members of both families are scheduled for release over the following twelve months.
The big FPGA companies have fended off repeated challenges by startups trying to join the programmable party. Over the years, process advantages, tool supremacy, and armies of AEs have provided a defensible perimeter for the two dominant players that have proven insurmountable for startups – even those with novel architectural ideas. Now, with two startups, Achronix and Tabula, both having access to Intel’s advanced process technology, there is a breach in at least one line of defense in those fortresses. It will be interesting to see what impact this has on the core FPGA market and how the bigger companies will respond to the challenge. Maybe Intel will be getting a couple more phone calls in the coming months. Maybe they already have.