feature article
Subscribe Now

The Return of Alchemy

XMOS Turns Software Into Hardware – Presto!

Subtle definitions can make a difference. The old song title, “What Is This Thing Called Love” is a lot different than asking your spouse, “what is this thing called, love?”

So it is with XMOS’s new chip, the XS1. Is it an FPGA or a microprocessor? Perhaps it’s the much-touted system-on-a-chip? Maybe an ASIC replacement? Or possibly something entirely different? By the time you’ve finished the 15-second elevator pitch, you’re already confused. What is this thing, how does it work, and how do I use it in my design?

Whatever taxonomic phylum the XS1 occupies, it’s an interesting device that’s worth a serious evaluation. We’ll start with the easy stuff: it’s cheap. With prices starting at less than $5 in quantity, the XS1 chip is not a BOM-buster. It’s also not large, coming as it does in a 96-pin dual-row BGA package about the size of a nickel.

But what role does it occupy in the broad spectrum of digital components? Is it an interface chip, a processor chip, or a logic chip? Do I program it, design it, or just plunk it down and forget it?

Well… all of the above. You see, the XS1 is a logic chip (like an FPGA) that you program in C (like a microprocessor). And once you’ve done that, well, you’re done. You can reprogram it if you like, but in most cases you’ll design/program it once and then forget about it.

So it’s sort of a C-programmable, field-programmable gate array. But inside, it’s really a microprocessor with a lot of I/O. It fulfills the role of PLD or FPGA on your printed-circuit board, but you talk to it with a C compiler, debugger, and code profiler. It’s a hardware device for software geeks. Or a software engine for hardware interfaces. It’s a crossover, like the Ford Flex or BMW X6 but not as ugly.

If you’re unfamiliar with XMOS and the XS1 chip, you’re in good company. The Bristol, UK–based company has been around since 2005 and employs about 40 souls (i.e., not counting the marketing staff). Despite its name, the new XS1-S is actually the third generation of XMOS’s difficult-to-pigeonhole chip family, its ancestors bearing the monikers XS1-L and XS1-G.

All three generations work pretty much the same way. They use an internal multithreaded microprocessor to “fake” the functions of programmable logic. In other words, the processor – entirely under software control – wiggles the chip’s I/O pins in whatever way you define. And you define those functions entirely with C code. There’s no schematic, no logic-design software, no drag-and-drop peripheral manipulation. It’s just straight C programming—for hardware.

The result is a user-defined logic chip that looks and acts just like a hardwired logic chip, except that it isn’t hardwired. You could also say it looks and acts like an FPGA or PLD, except there are no field-programmable gates or programmable logic. C code in; hardware functions out. That’s what the XS1-S does.

The internal structure of the XS1-S has no lookup tables, no fuses, no SRAM-based interconnect, nor any of the other hallmarks of a modern FPGA or PLD. It doesn’t need them. In lieu of the conventional sea of uncommitted gates, the XS1-S has the aforementioned microprocessor and a lot of uncommitted I/O pins on the package. The CPU runs at a steady clock rate of about 700 MHz, and it can toggle the state of any I/O pin on any clock edge. That’s plenty fast enough for Ethernet, USB, audio input/output, PWM, or just about any other digital-domain signal you might imagine. The cool part is, you get to define what those interfaces are and what pins they’re attached to. You also get to change your mind as often as you’d like, redefining peripherals as easily as updating a boot ROM. Want to invent your own proprietary external interface? No problem. Want to stick with industry-standard connections? That’s easy too, as XMOS provides code libraries for all the usual interfaces.

It gets better. Because all the I/O is handled by a processor, your peripherals can be smart. In a sense, each and every I/O interface is backed up by its own dedicated I/O processor that can massage data, filter inputs, encrypt or decrypt packets, and more. The processor is just as happy to do processing as it is handling I/O tasks, so the XS1-S is both a processor chip and a logic chip in one.

About the only special-purpose logic on the chip is the 480 Mbit/sec USB PHY and a four-channel ADC (12 bits, 1M samples/sec). There’s also the usual assortment of on-chip timers, power-management stuff, and buffers, but apart from that, it’s all under software control.

The processor itself runs eight threads, so you’ve got eight virtual processors at your disposal. In fact, XMOS says that’s the best way for new programmers to approach the device: think of it as eight independent CPUs, each running at one-eighth of the chip’s overall clock frequency. There is no elaborate time slicing or preemptive multitasking; the XS1-S chip simply shifts to the next thread on each clock cycle. Task 1 gets one clock tick, then Task 2 gets one clock tick, and so on. It’s extremely simple, very predictable, and totally deterministic.

If you’re an engineer of a certain age (ahem), you may remember Scenix Semiconductor (now called Ubicom). Scenix developed a “virtual” microcontroller that worked similarly to XMOS’s XS1 family. The Scenix chip looked like a typical Microchip PIC to the programmer, but inside, it really had a high-speed processor emulating all the peripherals. Like XMOS, Scenix provided an assortment of “soft peripherals” in the form of pretested software libraries that you could link into your application code. As long as you didn’t exceed the chip’s memory capacity or performance limitations, you could emulate just about any peripheral mix you wanted. It was a very clever concept, but one that didn’t pan out very well for Scenix.

For starters, the Scenix chip was too expensive for what you got. Basic PIC microcontrollers were dirt cheap in those days (and still are), so offering a more-expensive, albeit more flexible, variation was a tough sell. The Scenix device was good for early prototyping when you still weren’t sure what peripherals you’d need, but once your design was frozen, it was usually cheaper to find a normal fixed-function microcontroller with the right mix of peripherals. Flexibility and programmability were nice, but only up to a point.

In contrast, XMOS’s XS1-S doesn’t compete directly with anything. Although it’s microprocessor-based, it’s not another ARM, MIPS, ColdFire, or PowerPC knockoff. It more closely competes with FPGAs and other logic devices, where it stacks up pretty well. The single-digit price tag is a good starting point, but it’s the C programmability that really sets it apart. If you’ve got a software-oriented development staff, this may be the chip of your (or their) dreams. No one has to look at a schematic; the XS1-S is a hardware device for software guys. It can also compete with some DSPs and MSPs, such as TI’s MSP430 family, ST’s STM32 line, or Freescale’s DSP56K series.

The fact that XMOS has survived for seven years and is on its third generation of devices says they must be doing something right. The company claims to have more than 1,000 happy customers, and it’s upgrading its outsourced chip manufacturing to more advanced silicon processes. Maybe there’s something to this software programmability after all. 

2 thoughts on “The Return of Alchemy”

Leave a Reply

featured blogs
Nov 22, 2024
We're providing every session and keynote from Works With 2024 on-demand. It's the only place wireless IoT developers can access hands-on training for free....
Nov 22, 2024
I just saw a video on YouTube'”it's a few very funny minutes from a show by an engineer who transitioned into being a comedian...

featured video

Introducing FPGAi – Innovations Unlocked by AI-enabled FPGAs

Sponsored by Intel

Altera Innovators Day presentation by Ilya Ganusov showing the advantages of FPGAs for implementing AI-based Systems. See additional videos on AI and other Altera Innovators Day in Altera’s YouTube channel playlists.

Learn more about FPGAs for Artificial Intelligence here

featured paper

Quantized Neural Networks for FPGA Inference

Sponsored by Intel

Implementing a low precision network in FPGA hardware for efficient inferencing provides numerous advantages when it comes to meeting demanding specifications. The increased flexibility allows optimization of throughput, overall power consumption, resource usage, device size, TOPs/watt, and deterministic latency. These are important benefits where scaling and efficiency are inherent requirements of the application.

Click to read more

featured chalk talk

Shift Left Block/Chip Design with Calibre
In this episode of Chalk Talk, Amelia Dalton and David Abercrombie from Siemens EDA explore the multitude of benefits that shifting left with Calibre can bring to chip and block design. They investigate how Calibre can impact DRC verification, early design error debug, and optimize the configuration and management of multiple jobs for run time improvement.
Jun 18, 2024
41,669 views