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MATLAB to Hardware

MathWorks Automates HDL Creation

Quick! What’s the fourth largest EDA company in the world? Most of us in the industry can rattle off the “Big 3” right? “Daisy, Mentor, Valid.” Oops, my time machine was off by about 30 years. How about “Synopsys, Mentor, Cadence”? After that, it gets a bit dicey – if we counted Magma, that would be a possibility, but we need to chalk them up to Synopsys now. For those of us who think FPGA companies are actually EDA companies with a different business model, Xilinx and Altera would be in the top four or five. Beyond that, it drops off — a lot.

Most people would not immediately say “MathWorks”. In fact, even MathWorks would not say “MathWorks”. However, a growing but still unknown part of the company’s around $600M annual revenue is derived from tools that directly apply to electronic system design – both hardware and software. The company was founded on the lucrative principle of doing math for everyone, but math for electronic design turns out to be some of the most profitable math around. As a result, MathWorks has been playing an increasingly aggressive role in recent years – winding their way down from differential equations to DSP, and from simulations and graphs to working hardware.

This week, MathWorks introduced HDL Coder – which automatically generates synthesizable VHDL and Verilog directly from MATLAB. This introduction tears down some of the existing walls in many electronic system design houses. Typically, “someone” wearing long-flowing robes sits away in an ivory cubicle all day – experimenting with algorithms in MATLAB. That “someone” doesn’t do HDL. They don’t even do fixed point. They spend their time adjusting coefficients, evaluating alternative algorithms, and doing their darn-theoretical-best to get the future system fine-tuned to perfection. They polish their algorithm until it glows – eking out every ounce of efficiency and elegance from the formulas and equations that form the basis of their design. They place their perfected conceptual jewel in a velvet-lined box inlaid with exotic hardwoods and precious metal appointments. They emerge from their cubicle with music of violins and inexplicable beams of light illuminating their creation from the heavens.

Then, our special “someone” sends this prized package down the aisle to the hardware and software engineering teams – who proceed to attack the box with Sawzalls, sledgehammers, and pile drivers – re-doing the floating point in fixed point, re-coding the algorithm in HDL, and doing all manner of evil pipelining, resource sharing, unrolling, and re-jiggering – until the hardware version of the thing bears no resemblance whatsoever to the original, optimized, algorithmic amuse bouche. Except, of course, that it happens to sort-of do the same function. 

“Someone” is usually not bothered by this defacement of their work. They’ve long since returned to their lair and begun working on the next version of the algorithm.

Now, Mathworks has built some automation and accountability into this process. Yep, that means you can put away the Sawzall (dang, I know – that was a fun part for me too). HDL Coder generates both portable HDL and testbenches directly from both MATLAB and Simulink. At the same time, Mathworks announced “HDL Verifier” which provides FPGA-based hardware-in-the-loop capabilities. This allows execution of the algorithm you’re evaluating to be done at hardware speeds, allowing a much more exhaustive set of stimulus and test data to be applied. 

So, to summarize, you can start in MATLAB or Simulink and go directly to synthesizable, simulatable HDL, and then to an FPGA-based hardware-in-the-loop prototype platform. When you change or tune your algorithm in MATLAB, you don’t have to go back down the hall to the ivory cubicle, break out the pile driver, and re-do all your HDL coding work. HDL Coder can re-generate HDL, and you’re back in the evaluation part of the loop quickly.

This should dramatically accelerate the iteration loop for algorithmic designs or subsystems – particularly those that are datapath-oriented (such as signal processing.) Auto-generation of HDL generally makes synthesis and timing closure easier (as we human coders tend to push things pretty hard on the levels of logic and critical paths). Furthermore, it adds a level of rigor to our design flow that makes it easier to conform to high-reliability standards like DO-254.

MathWorks has partnered with both Xilinx and Altera on this project, has actually automated the flow with both vendors, and supports a number of FPGA development boards for the hardware-in-the-loop function. They have also partnered with a number of EDA suppliers including Cadence (Incisive), and Mentor Graphics (ModelSim and Questa) for support of co-simulation interfaces to MATLAB and Simulink for FPGA hardware-in-the-loop verification (through HDL Verifier). 

All of this partnering means that you can use the most popular FPGAs and development boards, along with the most popular simulation engines, and enjoy the new capabilities of HDL Coder and HDL Verifier.

Taking this discussion one level deeper – we wondered how HDL Coder compares with “high-level synthesis” tools currently on the market. Indeed, much like high-level synthesis tools, HDL Coder is converting un-timed algorithms (captured in MATLAB) to specific, timed microarchitectures in HDL. High-level synthesis tools do that and quite a bit more – including user-controlled architectural exploration, flexible memory generation, and interface synthesis. However, in our brief demo, HDL Coder offers control over the most commonly used datapath optimizations like pipelining, resource sharing, and loop unrolling. HDL Coder also offers both manual and automatic floating- to fixed-point conversion. That capability alone will expedite many design flows, as getting bit-widths optimized for your desired dynamic range is a bit of a tricky art all in itself. Is HDL Coder a replacement for high-level synthesis? No. Will it give you a lot of the same capabilities with less hassle? Probably so. 

For hard-core custom chip designs, teams may still often end up doing hand-coded optimization of their HDL code. However, for most prototyping and FPGA work, HDL Coder should provide an express lane from algorithm to implementation, and it should allow us to try a lot more variations and iterations on our design before settling in on our favorite. It should also make the path from algorithm to verified hardware much more deterministic – giving us peace of mind that our design actually implements the thing we simulated in MATLAB or Simulink. 

MathWorks says that HDL Coder and HDL Verifier are available now, with list prices for HDL Coder starting at $10K USD and for HDL Verifier at $3250 USD. While these prices are pretty steep for the typical MATLAB “I just wanna do math” user, they are relative bargains in the world of automated algorithm-to-hardware tools. 

14 thoughts on “MATLAB to Hardware”

  1. This is very complementary functionality to System Generator from Xilinx. HDL Coder 2012A also introduced interoperability with System Generator that allows both environments to be used together. Xilinx customers can continue to develop designs in Simulink using our device optimized Xilinx DSP blockset that includes IP compilers such as the FIR and FFT while creating new blocks using untimed, floating-point MATLAB. It also provides a direct path from MATLAB to Xilinx programmable logic for rapid prototyping that is not directly available in System Generator.


  2. Tom is correct, and the new interoperability helps users combine the complementary capabilities of both products, including:

    – MATLAB support: HDL Coder can be used with an algorithm written purely in the MATLAB language without using Simulink.
    – Simulink blocks: HDL Coder works with models built from standard Simulink blocks. With System Generator, you build models using Xilinx-specific blocks.
    – Device-independence or device-specificity: HDL Coder generates portable HDL code for FPGAs or ASICs. System Generator gives fine-grained control over the detailed settings of DSP blocks available in Xilinx FPGAs.

  3. “Is HDL Coder a replacement for high-level synthesis? No.”

    Can you tell me why, especially after HDL Coder added something like directive to control the arch-exploration?

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