Is it just me, or is digital design getting a lot trickier? We were all going along just fine, flipping our little zeroes and ones happily back and forth, and then somebody comes up with the brilliant idea to replace our nice, simple parallel busses with serial IO. OK, so maybe those parallel busses were not quite so simple by that time; it was starting to be nearly impossible to do the board layout so that all those signals arrived at somewhat the same time. To make matters worse, we kept raising the clock frequencies until “somewhat the same time” wasn’t even close to good enough anymore.
So, here came high-speed serial interfaces. That should be good, right? For the minimal design overhead of serializing and de-serializing our data streams, we got the wonderful benefits of drastically reduced pin and trace counts, and we got to stop worrying about timing out those big wide busses. But, we just couldn’t leave well enough alone. As soon as these SerDes connections started working pretty well, we bumped up the data rate – a lot.
As we entered the realm of multi-gigabit SerDes, those signals started to act a lot more like analog design than like digital design. Our reprieve from complicated board design lasted only a short time, because now instead of trying to get timing right on wide parallel busses, we were messing around with eye diagrams and bert scopes and all this fussy signal integrity stuff. FPGAs, which had been so good to us in the past, took on a more sinister role, as vendors packed on multi-gigabit transceivers to blast signal integrity problems onto our boards at new and ridiculous speeds.
New tools emerged to help us with these new problems, of course, like the HyperLynx tool from Mentor Graphics. HyperLynx helped to solve the signal integrity issues and gave a nice lift to our efforts to conquer signal integrity demons in our board designs. It’s a good thing too, because multi-gigabit SerDes went quickly from exclusive, high-end technology right into the mainstream market with standards like PCIe gen 3 and DDR3 and upcoming DDR4 memories. Now, you have to contend with signal integrity to design just about anything interesting.
But high-performance design was just getting started giving us fits. Remember when vias were just simple constructs, and we could throw them down just about anywhere on our board without thinking? It turns out that at really high frequencies, nothing short of a full 3D model with wave solvers will give us an accurate picture of what’s going on at those vias and help us figure out where and where not to put them.
Oh, and power and ground planes? Yeah, those broke too. Is nothing sacred? We used to be able to slap a big layer of pure metal on our board and plumb up all those pins that needed V-this or V-that to the appropriate one with little concern for anything. That was before we shrank our board, increased our operating frequencies, and poked about a million little via holes through most of our layers. Now there are all kinds of little unwanted current bottlenecks in our power and ground planes, and we need another field solver to make sense of it all.
At the same time, shrinking our boards and packing the components in tight has started to pile on the heat. As our designs have gotten faster, they are also needing more aggressive power and thermal management. Unless you have the luxury of an in-house thermal expert to come model and analyze each of your designs, you need a way to get a handle on the hot spots before you accidentally build something you’re not so happy about.
Mentor Graphics has just announced a new version of HyperLynx (8.2) that helps address these new problems as well. In addition to the existing signal integrity stuff, they’ve added in a full 3D full-wave field solver that can accurately model the effects of structures like vias at critical data rates in the 5Gbps to 28Gpbs range. The new system partitions the key structures like vias into special areas for full 3D analysis, while keeping compute times under control by continuing conventional 2D analysis of the non-critical structures.
HyperLynx 8.2 also includes power distribution network (PDN) analysis that can co-simulate between power integrity DC and thermal analysis to help us locate those new hot spots in our power planes. Combining these analysis modes allows a fairly complete view of the performance of our power planes and helps spot areas where neck-downs might be hurting our power integrity or causing excessive heating.
One of the advantages Mentor brings to this analysis realm is the integration of these often-separate tools with the rest of your PCB design flow. Each of these analysis tools is available separately from various vendors, but dynamically creating the required models and passing the data back and forth from tool to tool – particularly if you’re in a design phase where you’re iterating your design to attack specific thermal, power, or signal integrity problems – can become more work than doing the analysis itself. The clean integration between these functions in Mentor’s suite prevents us from having to become EDA software developers as well, wrapping scripts and homemade data converters around our point analysis tools.
Mentor’s HyperLynx is available in a wide range of capabilities and price points. The new version – 8.2 – will start volume shipment in February 2012. That means you could start using it on the design you’re doing right now.
As we keep packing our designs tighter, running more IOs at even higher data rates, expanding the number of power rails in our designs, and reducing our supply voltages – problems like signal integrity, power integrity, and heating will just get worse. Furthermore, as new high-speed standards like PCIe gen 3 become commodity, even mainstream and commodity designs will need access to the kind of analysis capabilities coming into HyperLynx. We expect to see a lot of interest and growth in high-performance board analysis tools like this over the next few years.
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This week, we took a look at Mentor’s latest version of HyperLynx and how it helps with signal integrity, power distribution network analysis, 3D via modeling, and thermal issues.
Are you starting to face some of these issues in your FPGA-based board designs?