feature article
Subscribe Now

Extreme Exposure

EUV Seems to be Coming Around

EUV is one of those topics that people have been talking about for a long time, and there’s been a long list of challenges in getting it to work. So imagine my surprise on watching a Semicon West session and learning that EUV is actually being deployed – with caveats – today. That got me wanting to go back and figure out what the issues have been and how they’ve been addressed.

But let’s back up a second to make sure everyone’s on the same page. We’ve been using visible light for lithography for far longer than we should have been able to. We’ve been exposing features that are far smaller than the 193-nm wavelength of the ultraviolet light being used to expose wafers, something we shouldn’t have been able to do.

Of course, we’ve played tricks to extend the reach of this technology, partly by using immersion in water to improve the index of refraction and partly by playing around with the mask patterns – essentially pre-distorting them to account for the impact of exposing such small features.

But we’re reaching the limits of our tricks. We really will need something to get to single-digit dimensions, and, even before that, the cost of multiple-patterning will make EUV look less expensive than it looks now. The conventional expectation is that a shorter wavelength will let us expose smaller features – hence extreme ultraviolet (EUV). Unfortunately, it’s not that simple – in fact, it’s been work to get resolution of EUV low enough even to match that of 193 nm.

And that’s but one of the challenges. If you search the internet for information on EUV technology, you will find objection after objection and problem upon problem that may well convince you that this technology will never see the light of day. So it’s really hard to square that with the Semicon West presentations I saw.

One of those presentations was by Dr. Stefan Wurm, Associate Director of Lithography at Sematech. Because his and the other talks were mostly directed at those following developments closely and who were therefore current on the subject, I talked to Dr. Wurm separately after the conference to get a bigger-picture perspective on what’s going on.

There are four critical components to an EUV system:

  • the source of the EUV light;
  • the optics – that is, how the EUV light gets delivered to the wafer;
  • the masks;
  • and the photoresist.

Each of these has issues that are still being worked.

The source is the obvious new component, and the current challenge can be summarized in one word: power. We’re going to look at how to generate the EUV light in more detail in a separate upcoming article, but suffice it to say that, for now, it works. It just doesn’t work “hard” enough to give the throughput needed to do high-volume manufacturing (which is such an important concept in this field that it merits its own TLA: HVM).

Exposure of wafers is done a “field” at a time, stepping across the wafer until it is completely exposed. A field contains some integral number of dice (so there are no overlap issues at actual circuitry). Clearly, the bigger the field that can be exposed in the fastest possible time, the faster you’ll get through a wafer. And that takes power.

The optics are different for EUV: because so much light is absorbed at these wavelengths, all guiding is done by reflection, not refraction. Meaning mirrors instead of lenses. There is a “collector” that gathers the emitted EUV radiation and focuses it on a target. And this all more or less works and isn’t specifically a roadblock at present. Efficiency (collecting as much light as possible) and keeping it from dispersing require ongoing care, however.

Mask quality is a big issue. In fact, for a while, simply having a way to inspect masks was a barrier. That’s been overcome, and, for the most part, we’re now in a learning mode to get mask quality where it needs to be.

And that leaves resist. The lowly goop that coats the wafers and preserves the impression that the light exposure creates. I don’t know about you, but, for me, it’s always felt like resist is resist is resist. Which couldn’t be further from the truth.

Resist design has borne the burden of solving a number of vexing issues. One of those is secondary electron scattering. The problem is that EUV photons, by definition, are rather excited when they reach the wafer. And that excitement is contagious, rubbing off on the electrons that they interact with, and those electrons go flying off in various directions until they finally calm down and behave decently again.

The problem is that, by the time the electrons stop, they’ve traveled rather far from where they started; this “secondary electron border” totally screws up the attempts at exposing small features and also contributes to line-width roughness (which also gets a TLA: LWR; it’s also sometimes called line-edge roughness, or LER). The nature of the resist plays a role in how far those electrons go.

Also important is the diffusion of acids created by EUV exposure. This needs to be limited to keep the exposure edges sharp.

There’s an additional issue with the stiffness of the resist. As the features shrink, the resist layer has to get thinner or else you end up with these tall thin strips of resist that have a tendency to fall over. A 2.5:1 aspect ratio is targeted, but better stiffness is desired.

The bottom line is that resists need to strike a balance between resolution, sensitivity, and line-width roughness, and that involves tradeoffs in all three directions. I even saw a reference to a so-called “Z-factor” that acts as a figure of merit for the three combined characteristics:

(half-pitch)3*(LWR)2*sensitivity

By playing with the polymer size, trying to create a hybrid between traditional “chemically amplified resists” and inorganic resists (some of which have tighter resolution at the cost of sensitivity), playing with the quencher distribution (which “quenches” the reaction and neutralizes the acid produced by exposure), and optimizing such process steps as the rinse and etch steps, LWR can likely be taken from 4 or 5 nm, where it is now, down to around 3. For perspective, the ITRS roadmap is looking for 1 nm, so there’s more work to be done.

So, with all of these issues remaining, how is it that systems are being shipped? Well, the caveat is that they’re beta systems, more or less. Very expensive beta systems, to be sure. And, traditionally, fabs will bring up a new technology on an existing node to learn how to do it before deploying the technology on the next node.

Memory makers will be able to use this stuff first. Because of their regularity and the use of redundancy, they can tolerate a less mature process better than logic can. Foundries are likely to jump on board next in order to avoid the cost of implementing multiple patterning. Pure logic IDMs are seen joining the party last.

The first production tools are expected to be delivered late 2012 or early 2013; there are 8-10 units on order. Confidence is higher now since, while issues remain, there are no longer any specific roadblocks that remain unresolved or have no owners.

So, contrary to what you might read on the interwebs, it does appear that EUV may truly be coming to a fab near you.

Leave a Reply

featured blogs
Jul 3, 2020
[From the last episode: We looked at CNNs for vision as well as other neural networks for other applications.] We'€™re going to take a quick detour into math today. For those of you that have done advanced math, this may be a review, or it might even seem to be talking down...
Jul 2, 2020
Using the bitwise operators in general, and employing them to perform masking operations in particular, can be extremely efficacious....
Jul 2, 2020
In June, we continued to upgrade several key pieces of content across the website, including more interactive product explorers on several pages and a homepage refresh. We also made a significant update to our product pages which allows logged-in users to see customer-specifi...

Featured Video

Product Update: DesignWare® TCAM IP -- Synopsys

Sponsored by Synopsys

Join Rahul Thukral in this discussion on TCAMs, including performance and power considerations. Synopsys TCAMs are used in networking and automotive applications as they are low-risk, production-proven, and meet automotive requirements.

Click here for more information about DesignWare Foundation IP: Embedded Memories, Logic Libraries & GPIO

Featured Paper

Cryptography: Fundamentals on the Modern Approach

Sponsored by Maxim Integrated

Learn about the fundamental concepts behind modern cryptography, including how symmetric and asymmetric keys work to achieve confidentiality, identification and authentication, integrity, and non-repudiation.

Click here to download the whitepaper

Featured Chalk Talk

Avnet and Samtec Enable System-Level Exploration with new RFSoC Kit

Sponsored by Samtec and Avnet

5G infrastructure presents daunting challenges on the RF front. We want to put the processing as close as possible to the antenna, and the standards are evolving so fast that programmability is a must. In this episode of Chalk Talk, Amelia Dalton chats with Matt Brown from Avnet and Matt Burns from Samtec about the Avnet Zynq Ultrascale+ RFSoC Development Kit, which brings the power and flexibility of an FPGA-based RF front end to your lab bench.

Click here for more information about the Avnet Zynq Ultrascale+ RFSoC Development Kit