Intent matters. Not as much as results, but it does matter. And it should drive results. These days, higher levels of design abstraction make it easier to express design intent rather than simply keeping it in your head (or in a document if you’re diligent) and implementing the intent directly. Behavior is an obvious example of logic intent, but that’s old news. Power is much more in vogue these days.

And we have a standard for that. No, wait, we have two standards, UPF and CPF. At least for the time being, as there are attempts to resolve them into one (or eliminate one, depending on how you look at it). They’re not isomorphic, but they’re close, even if they’re skinned with different syntax. Yes, syntax: these are text files. Numerous tools accept one or the other or both as input, helping to inform the functionality of the tools. Many other tools, when synthesizing or optimizing or modifying the design, will back-annotate the UPF or CPF file to reflect the changes made.

But, absent any other help, it’s up to the architect or designers to create the original file. Now… I know it’s a sign of extreme manhood to find the hardest possible way to do things, insisting it’s best, and then to take pride in slogging through the process with minimal calamity. I’m sure Bear Grylls would prefer text editing one of these files – hell, he’d probably write it using ASCII code switch-by-switch on a PDP 11 he happened to have in his backpack from inside a cave he hewed out of solid granite with his teeth, while generating power on a bicycle he assembled from twigs and guano, eagerly waiting to run out of water so he could gross everyone out. Again. Well,  except when he’s staying in a 5-star hotel. But on the occasion he would come out because the cameras were rolling, then yeah, he’d definitely do it that way.

But he doesn’t have to ship a chip to customers. And, OK, maybe it’s not that hard. In fact, according to Barry Pangrle, a low-power solutions architect at Mentor, they’re not hearing customers complain. Most of their customers use the UPF file at the RTL level, by which point you’re well into implementation. He can see the utility at the architectural level of something more abstract than a text file, and Mentor is checking with customers on such a feature. But that’s a future thing for them.

Synopsys, on the other hand, was convinced earlier that things could be made easier. Last year they released their Design Vision tool, which allows designers to create and view a UPF file. The idea is to be able to visualize better the relationships within the circuit for verification and debugging purposes. The circuit can be viewed hierarchically, or you can identify the various parts of the circuit under the dominion of a given power supply.

This certainly takes things up a step from text editing, but, more recently, Cadence drove this even further, albeit with the CPF file, which is their baby. Although… there are cracks in their staunch fidelity… but I’m getting ahead of myself.

Cadence is focusing on the high-level architecture and, in particular, on the significant challenges of bringing together numerous IP blocks, each of which may have several power modes and an associated CPF or UPF file. They’ve released a tool called Power Intent Architect to help designers manage these challenges.

Their canonical model starts with their ChipEstimate facility, which allows early experimentation with different architectural and IP options. ChipEstimate can now create a high-level CPF file that can then be refined in Power Intent Architect. Alternatively, you can pull in an existing design and then start working on the power elements. You can do it flat or hierarchically.

It’s actually possible to optimize IP blocks if certain available modes won’t be used in the design: the circuitry needed to support those power modes can be eliminated, reducing the size of the chip.

Hard IP can be a bit trickier, since, by definition, implementation is complete on that block. So a power intent model doesn’t help from a design creation standpoint, but it does help for overall power verification of the entire chip.

The creator of a custom hard IP block can use Virtuoso to abstract out the power intent of the block into a model that can then be used by the chip architect or integrator. If that’s not available, then, as a user of the IP, you have some ability to trace power nets to derive power intent, but things like level shifters will make it hard to do a thorough job on anything really substantial. The Liberty models also have some power information in them, identifying regular vs. low-power transistors and calling out level shifters, but this is a subset of what’s available in a full power intent file. Nonetheless, Liberty files can be pulled into Power Intent Architect to help fill in as many pieces of the puzzle as are available.

Given all of these blocks and their power intent information, they can be integrated bottom-up into a complete circuit design intent file. For parts of the design that must be created afresh, you can also partition top-down to create the specific power intent information for lower-level blocks before handing them off to the engineers that will do the implementation.

The power intent not only drives design creation, but it also allows full verification to ensure consistency and correctness. Further down the design cycle, the file can be used as a golden reference to confirm that there was no corruption in any of the synthesis steps and that there are no ground or short problems or other such mistakes.

And Cadence has done this with a surprising ecumenical angle: Power Intent Architect will create both CPF and UPF files. Of course, they refer to the CPF as the golden reference, but, for those tools in your flow requiring UPF, a UPF file will be provided as well. This is interesting, in that Cadence has been a steadfast promoter of the CPF file, bearing up against the pressure of the other big guys that support UPF. You could smirk, or you could simply say, “Good on ya for putting the practical needs of users first.”

While going GUI often has the feel of simply making things a little bit easier, the kinds of productivity gain made possible by something like this, thanks to the management of many different contributing sub-files, open up the possibility of spending time on real power optimization and verification rather than the drudgery of managing text files. If that’s the case, my guess is that you’ll see the others move in this direction as well.

More info:

Cadence Power Intent Architect (part of Conformal Low Power)

Synopsys Design Vision (part of DC Ultra)