feature article
Subscribe Now

Banner Year

2010 in FPGAs in Review

Ring the bells, tell the tales and calibrate the scales.  2010 is coming to a close and the FPGA market will never be the same.

On the other hand, the FPGA industry was never the same before 2010, so this is probably business as usual.

2010 saw the real rollout of FPGA families that were introduced last year – 40/45nm products from Xilinx and Altera; creative alternative products from Actel, Lattice, and QuickLogic; and 65nm products from SiliconBlue and Achronix.  Real customers are now using real versions of all these parts, and the results are – similar to what we all predicted the previous years when they were announced.

Industry-wide FPGA sales are reported to be up a staggering 47% for 2010.  In a sluggish global economy, that’s a doubly exciting double-digit figure.  However, the boom year for FPGA sales has absolutely nothing to do with this year’s “news.”  2010 revenues were actually made in 2008, when the chips that are now being ordered and delivered in volume were designed into systems.  As much fun as we have writing about 40/45nm FPGAs and even 28/22nm FPGAs, the big numbers in 2010 are more due to the success of the 90nm and 65nm products that we in the press have long since abandoned.

This leads us to a modest proposal for 2011.  How about the FPGA marketing folks take the year off?  In fact, we think a plan where FPGA marketing worked only every other year would be ideal.  The “off” year could be the year that each new process generation is currently “announced.”  That year is a marketing throw-away.  This year, Xilinx and Altera both rolled out big 28nm announcements – but nothing “real” will actually happen there until late 2011 or early 2012.  FPGA marketing people could have taken 2010 off, come to work on Jan 1, 2011, and started putting together launch materials for 28nm – by fall 2011 they could have been ready to announce – and it would have been exciting!  New chips – that you can buy!  Then they could spend the rest of the year documenting and promoting the cool things customers have done with the chips they sold last year.  Then, they can take a year off. 

Too bad Moore didn’t make his law based on the annual rate of growth instead of bi-annual.

What we did get this year, however, is pretty exciting.  With the continuing rise of mask costs and NRE, the number of companies that can afford to build custom chips for specific applications is declining rapidly.  However, the integration required in today’s electronic products continues to rise.  Most competitive products today involve a system-on-chip SoC of some sort – surrounded by some peripherals that were missing from the SoC.  So – designers need to be able to realize their applications with SoCs, but for most of them, designing an SoC is far too expensive.  The result is that we have to either force-fit our applications into ASSPs or make our own SoCs using FPGAs.

28nm FPGAs are the most impressive “roll your own SoC” devices the world has ever seen.  (Even though the world hasn’t actually seen them yet).  The density, speed, power consumption, and IO capability of these devices will be truly remarkable, and the cost-per-gate to design your own reprogrammable SoC has never been lower. 

On the high end, we’ll have Xilinx and Altera building parts on TSMC’s latest-generation 28nm processes. Plus, we’ll have the new dynamic duo of Achronix and Intel marketing and making 22nm high-speed asynchronous FPGAs.  In fact, Intel’s toe seems firmly dipped into the FPGA pool at this point, and we’re very curious to see if the ankles follow.  In addition to the announcement that Intel will fabricate high-performance FPGAs for Achronix using their latest-greatest process, they also announced their own new “Stellarton” line of processors that combine an Atom processor with an Altera Arria FPGA in one package.  It makes sense, given the 47% growth rate above and the fact that FPGAs are among the highest-margin silicon on the market (next to processors), that Intel would be wanting to play.  However, the FPGA market is a notoriously dangerous place – with the siren song of high growth and huge margins concealing the nasty sharp teeth of a software and support business masquerading as a chip business. For 2011 – we want to watch Intel’s interest in FPGAs evolve.  Will they jump in farther, or will they get spooked and retreat?

The new generation of high-end devices will all boast 28Gbps high-speed serial transceivers.  They will all support at least soft-core embedded processors, and many will contain hard-core optimized processor blocks – if not complete embedded processing subsystems.  They all will contain massive amounts of block memory – which will come in handy with all that embedded processing going on.  They will also all contain high-performance DSP blocks for building algorithm accelerators – taking advantage of the superior performance, power consumption, and density of optimized hardware multiplier blocks.

To really drive us to success with these impressive devices, though, the devil will be in the tools.  Previous-generation design tools are clearly not going to be up to the task.  Third-party EDA companies like Synopsys and Mentor Graphics have both begun announcing tools with greater capacity, greater performance, more flexibility for handling the complex IP that is used in these devices, and provisions for team-based design – which will almost certainly be the norm when tackling a giant system-on-FPGA as the centerpiece of a new product development project.  The FPGA vendors themselves have been hard at work improving the performance, quality-of-results, ease-of-use, and flexibility of their proprietary design tool suites as well. 

Beyond tools, we’ll also need IP aimed at specific target markets and reference designs for common applications that will get us 90% of the way to our finished application – with white space left over for us to add our proprietary, product-differentiating engineering brilliance.  In an ideal world, we could download the “standard” version of the product we’re building as a reference design, and then spend all our engineering time and energy just adding the secret sauce that makes our version special.  FPGA vendors won’t get us very close to that vision in the next year, but they are clearly headed in that direction.

On the low end – there is increased action as well.  Lattice, Actel, SiliconBlue, and QuickLogic all continued to pursue the “low” end of the FPGA market – with renewed competition from Xilinx and Altera.  SiliconBlue, Actel, Lattice, and QuickLogic have all put heavy emphasis on low-power, small form-factor devices suitable for battery-powered mobile applications.  These devices are about as far from the mind-bending high-performance FPGAs as you can get… and still be called an FPGA.  In this market, the priorities are microwatt static power, non-volatile configuration, tiny form factors (single-digit millimeters), and super low-cost (less than $10 and often less than $1 in production quantities).  The competition in this space is heavy – and these companies tend to differentiate their offerings by going after specific high-value target applications.  As examples, QuickLogic has concentrated on reducing power consumption and improving viewing quality on mobile displays, and Actel has pushed their Fusion series into control applications that take advantage of Fusion’s programmable analog features.

Xilinx almost fell out of the low-cost FPGA market with the stall of their Spartan-3 line and their complete lack of a 65nm low-cost family.  They picked the ball back up at 45nm, however, with Spartan-6 and have announced plans to continue with the upcoming 28nm families.  Altera’s Cyclone family has also suffered the “younger sibling syndrome,” yielding emphasis to the flagship Stratix-branded FPGAs.  Cyclone IV, for example, is not a full-fledged new-generation family, but rather a re-work of Cyclone III on the same process generation.  The low-cost families from Xilinx and Altera seem to aim a bit higher than the mobile-focused competitors.  The Spartan and Cyclone lines are not competitive at the super-low end with the specialized, microwatt-sipping, non-volatile, tiny-packaged, penny-priced parts from their more aggressive challengers.

As we’ve discussed in these pages before, Actel’s acquisition by Microsemi was also a banner event in 2010.  Those of us in the editor and analyst community are waiting to see where the other shoe falls, at this point.  On one hand, there is market compatibility between the offerings of the two companies, and Microsemi makes compelling arguments about how the product lines are complementary.  However, the FPGA business is a new and challenging arena for Microsemi, and many have failed where they are about to tread.  Only time will tell how this turns out.  Welcome to 2011!

Leave a Reply

featured blogs
Dec 7, 2023
Semiconductor chips must be designed faster, smaller, and smarter'”with less manual work, more automation, and faster production. The Training Webinar 'Flow Wrapping: The Cadence Cerebrus Intelligent Chip Explorer Must Have' was recently hosted with me, Krishna Atreya, Princ...
Dec 6, 2023
Explore standards development and functional safety requirements with Jyotika Athavale, IEEE senior member and Senior Director of Silicon Lifecycle Management.The post Q&A With Jyotika Athavale, IEEE Champion, on Advancing Standards Development Worldwide appeared first ...
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Power and Performance Analysis of FIR Filters and FFTs on Intel Agilex® 7 FPGAs

Sponsored by Intel

Learn about the Future of Intel Programmable Solutions Group at intel.com/leap. The power and performance efficiency of digital signal processing (DSP) workloads play a significant role in the evolution of modern-day technology. Compare benchmarks of finite impulse response (FIR) filters and fast Fourier transform (FFT) designs on Intel Agilex® 7 FPGAs to publicly available results from AMD’s Versal* FPGAs and artificial intelligence engines.

Read more

featured chalk talk

High-Voltage Isolation for Robust and Reliable System Operation
In this episode of Chalk Talk, Amelia Dalton and Luke Trowbridge from Texas Instruments examine the benefits of isolation in high voltage systems. They also explore the benefits of TI’s integrated transformer technology and how TI’s high voltage isolations can help you streamline your design process, reduce your bill of materials, and ensure reliable and robust system operation.
Apr 27, 2023