Designers have long understood how to use a single processor for the control functions in a SOC design. However, there are a lot of data-intensive functions that control processors cannot handle. That’s why designers design RTL blocks for these functions. However, RTL blocks take a long time to design and even longer to verify, and they are not programmable to handle multiple standard or designs.
Dataplane processors (DPUs) are designed to provide programmability in the performance-intensive dataplane of the SOC design. You can think of them as a combination of a DSP and a CPU – but they’re even better than that, as you can customize them for maximum efficiency for your target application. Need wide datapaths or instructions? Read more about how you can quickly get these built into your own DPU.
What is a DPU? What can DPUs do? Why would anyone want to use this type of processor? How can a DPU be used instead of creating hand-coded RTL hardware? These questions and more are answered in this white paper.
As shown in several examples, it’s possible to accelerate the performance of many embedded algorithms using customized microprocessor cores. Designers can add precisely the computing resources (special-purpose registers, execution units, and wide data buses) required to achieve the desired algorithmic performance instead of designing these functions in hand-coded RTL acceleration hardware.
This processor-centric design approach to ASIC design can be achieved by using profiling tools to analyze existing algorithm code to find the critical inner loops. This process is well understood by firmware-development teams. From these profiles, the ASIC design team can define new processor instructions and registers that accelerate critical loops. The result of using a configured processor is to greatly accelerate algorithm performance and produce a working function block in a much shorter time period than needed to design and verify an RTL accelerator block. In most cases, designers can use configured processors tuned for the exact application instead of hand-coded hardware accelerators, saving valuable design and verification time and adding an extra level of design flexibility because of the inherent programmability of the processor-centric design approach.
