Virtex-6 FPGA Routing Optimization Design Techniques

by Jim Turley

With the ever-increasing need for high bandwidth, system designers continue to increase resource utilization when designing with Virtex®-6 devices.

This can sometimes lead to routing challenges and congestion that can impact design closure. This white paper provides recommendations to help customers mitigate routing challenges in their Virtex-6 FPGA designs.

Xilinx continues to refine the place and route algorithms in each of the ISE® software releases and provides up-to-date information on additional design techniques to help customers optimize routing in their Virtex-6 FPGA designs, making it easier to reach performance and power design goals and achieve next-generation bandwidth requirements.

Author: Michelle Fernandez and Peggy Abusaidi, Xilinx

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Virtex-6 FPGA Routing Optimization Design Techniques

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