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Lattice Unveils MachXO2

CPLDs are Dead! Long Live CPLDs!

Lattice Semiconductor launched a new line of 65nm low-density programmable logic devices this week, putting an exclamation mark on the importance of the low-density programmable logic market.  By “low density” what we mean is – pretty high density by the standards of just a few years ago.  Lattice’s new family brings a 3x increase in logic density, a 10x increase in embedded memory, and significantly lower cost (the company claims “up to 30% lower”) compared with its predecessor, the MachXO family.

Lattice has been busy turning down the juice as well, claiming more than a 100x reduction in static power.  The result is a family of devices that is highly appropriate for high-volume, cost-sensitive, low-power applications like mobile devices.  They’ve added a number of features not normally found in devices of this class, such as hardened I2C, SPI, and timer-counters, as well as user flash memory.  Altogether, what we’ve got here is a device family positioned exactly in the spot traditionally reserved for CPLDs, but with a boatload more capability. 

The new family is implemented with 65nm embedded flash technology, and it is based on what we’d think of as an “FPGA” architecture.  The traditional CPLD architecture is becoming a bit of a dinosaur in all but the very lowest density applications, giving way to much greater density and capabilty with an FPGA architecture.  It could be argued that Lattice was the originator of the current three-tier model (low-density, mid-range, high-performance) that is used by most of the programmable logic industry today.  While the low-density end of the market gets the least attention in the press, it’s a very important segment of the market – accounting for a significant chunk of overall revenues.

In the low-density space, Lattice has always been one of the top competitors – battling it out with Altera for leadership, and clearly frustrating Xilinx with their prowess against that company’s “Coolrunner” lines.  Now, they’ve raised the ante with a family that could clearly gain them significant market share if the “big 2” programmable logic companies don’t respond quickly or adequately.  Now, instead of quietly sitting back and competing against other CPLDs, Lattice’s new family (with densities running up to 7K LUTs) slams right into the range of low-cost FPGA families like Xilinx’s Spartan, Altera’s Cyclone, and Actel’s (now Microsemi’s) ProASIC3 and Fusion devices. 

In some applications, MachXO2 will have significant advantages against those FPGA families in areas like static power (with static power ratings down in the low double-digit microwatts), cost (with prices well under a buck), and form factor (with packages as small as 2.5×2.5mm – “Whoops, dropped my FPGA – dang, we’ll never find it in this carpet!”).  Since the devices are non-volatile (based on a similar on-chip flash configuration architecture to Lattice’s popular XP and XP2 FPGA families), you won’t need extra configuration circuitry – saving more BOM cost and board space compared with low-end FPGAs. 

The new family comes in three flavors – MachXO2 ZE, HC, and HE.  The ZE devices range from 256 to 7K LUTs, use a 1.2V power supply, and operate up to 60MHz.  HC devices also range from 256 to 7K LUTs, but they operate off 3.3V or 2.5V power supplies with performance up to 150MHz.  HC devices also offer up to 335 user IOs.  The HE devices range from 2K to 7K LUTs, operate off 1.2V, and have performance up to 150MHz. 

The ZE devices will work best in cost-sensitive, power-sensitive, area-sensitive applications like mobile devices.  HC devices will shine in more demanding applications where higher frequencies and more voltage flexibility are required, and HE devices are optimized for low-power applications that still require higher-performance. 

In tiny devices like these, the trick is getting enough IOs around the periphery of the chip without making the die too big.  Lattice gets around this with three rings of IO staggered around the chip.  Since many of these devices end up in bridging applications, Lattice also uses a system of IO banks that help facilitate the use of multiple IO standards with a single device. 

Looking at the total system cost picture as well, the devices feature on-chip voltage regulation.  That means they will be pretty forgiving if your attention to power design on your board isn’t up to snuff. 

At the same time, Lattice is announcing full support for the new family in their recently-revamped “Diamond” design tool suite.  The new version of the design tools are available now, and they bring some additional goodies to the party, including a customer beta version of a new synthesis engine called “LSE” for “Lattice Synthesis Engine.”  The Diamond suite still includes OEM versions of Synopsys Synplify Pro synthesis and Aldec Active-HDL simulation, but an additional synthesis engine is always a good thing to have in your tool arsenal.

Also in keeping with Lattice’s practice of just-in-time announcement, the new family has devices available now as alpha samples, with engineering samples next month, and production in March, 2011.  The company says all members of the family are expected to be shipping in production volumes by the end of Q3, 2011.  That means that any competitive responses had better happen quickly, because these parts will be headed into a lot of systems right away. 

Lattice says pricing for the smallest HC and ZE devices (256 LUTs) in a TQFP100 package is $0.75, and pricing for the 1200 LUT version in a TQFP 100 package is $2.00 (both prices in 500K unit volume). 

Lattice seems to have turned a significant corner in recent times and is emerging as a leaner, more battle-hardened competitor in the FPGA and programmable logic space.  The company continues to find areas where they can differentiate themselves while still taking a primarily head-to-head position against their larger competitors.  Culturally, the company seems to have shifted as well – and for the better.  The new vibe at the company feels more focused on delivering useful technology to customers and finding ways to win by engineering better solutions.  We expect they will see the benefits in their results.

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