Across a range of applications, the two most common functions implemented in FPGA-based high-performance signal processing are finite impulse response (FIR) filters and fast Fourier transforms (FFTs). The FPGA’s digital signal processing (DSP) architecture must be optimized to allow the most efficient implementation of these structures as this directly translates into cost and power benefits to the customer. This white paper introduces the DSP architecture of the latest 28-nm Altera® FPGAs and shows how this architecture enables the most efficient implementation of FIR filters and FFTs.

Introduction

FIR filters and FFTs are two of the most common DSP functions implemented in FPGAS. As shown in Figure 1, Altera’s internal primary market research shows that these functions dominate implementation when it comes to DSP in FPGAs. This is most likely due to the fact that FPGAs alone are able to meet the throughput and latency requirements for these functions, given the parallel DSP datapath implementation that is feasible with the FPGA architecture.

Figure 1. Types of DSP Functions Implemented in FPGAs 

Given the preponderance of FIR and FFT implementation, it is critical that the FPGA DSP architecture be designed to enable this implementation with highest performance and the least resources. At the 28-nm process node, Altera has developed the FPGA industry’s first variable-precision DSP architecture in its Stratix® V devices. This architecture enables designs with varying precision and performance requirements to be implemented using the 28-nm silicon fabric with two to three times the implementation efficiency compared to competing, fixed-precision 18×25 DSP architectures.

This innovative 28-nm DSP architecture is also designed with key features that enable the efficient implementation of high-performance FIR filters and FFT structures. This white paper details the specific key features that are included for FIR and FFT implementation optimization.

FIR Filter Optimization Features

As shown in Figure 2, Altera’s 28-nm DSP architecture includes a host of features for optimizing FIR filter implementations:

• Hard, built-in pre-adders can be used when implementing symmetric filters to cut multiplier usage by half.
• Internal co-efficient register storage allows the designer to store the filter coefficients inside the DSP block, which not only saves registers and memory but allows for faster fMAX because coefficients do not have to be routed from the logic.
• Two levels of adders within a single block, which are important when building “direct-form” FIR filters. Competing DSP blocks have only a single level of post multiply adder stage, which necessitates external logic-based adders to build an adder tree.
• Output register and cascade path for implementing systolic filters.

Figure 2. DSP Architecture Features for FIR Filter Implementation
 

Author: Suhel Dhanani, Senior Manager, DSP Marketing, Altera Corporation

Suhel Dhanani is a senior manager in the software, embedded and DSP marketing group. Mr. Dhanani is responsible for DSP product marketing. He has over 15 years of industry experience in semiconductors with large companies such as Xilinx and VLSI Technology, as well as with Silicon Valley startups including Anadigm and Tabula. Mr. Dhanani has completed a graduate certificate in Management Science from Stanford University and holds MSEE and MBA degrees from Arizona State University.