As IC design teams adopt advanced process nodes, they are packing more functionality and performance into silicon. However, design challenges are growing as designers push the limits of performance, complexity, size, power reduction, and manufacturing scaling. Starting at 45/40 nm, the increasing complexity of DRC and DFM rules began to stress traditional physical design flows. This trend is expected to continue and worsen at the 32/22-nm nodes, where manufacturing closure may become a serious bottleneck in design schedules. Designers need a new generation of physical design tools to effectively address these issues.
Sources of DRC/DFM Closure Problems
The fundamental source of the recent DRC/DFM closure problem is the continued use of 193-nm light lithography to etch ever-smaller features. To maintain yield, IDMs and foundries are being forced to tighten up their design rules to ensure that physical features that are susceptible to these effects are not introduced into the design (Figure 1).
Figure 1. The difficulty of manufacturing at sub-40-nm nodes is forcing foundries to introduce many new design rules, and to make DFM analysis mandatory.
The number of DRC and DFM rules has at least doubled between the 90-nm and 32-nm nodes, depending on the foundry. The rule complexity, measured by the number of operations required to verify the rules, has grown even faster, as shown by the red bars in Figure 2.
Figure 2. The number of design rules, and the complexity of the rules, has risen steadily at each process node, leading to growing problems in design closure.
Typically, during physical implementation, simplified DRC and DFM models are used to provide the optimal trade-off between runtime and accuracy. Once the implementation is complete, the GDSII layout is verified using signoff-quality DRC/DFM models. At previous design nodes, this traditional flow was sufficient, but the rules at 32/28 nm are so complex that some cannot be effectively defined for physical implementation tools. DFM rules, which used to be recommended, are now becoming mandatory, forcing designers not only to meet performance, power and cost targets, but also to ensure that the design is manufacturable. In addition, the growing use of IP has exacerbated the problems because of outdated rules or mismatches between the abstracted cell layout view used in place-and-route and the complete GDS view used in signoff.
This disconnect between the implementation and verification environments has caused the number of DRC and DFM errors to increase significantly during signoff. The result is a time-consuming cycle of multiple, non-convergent iterations between verification and implementation in order to achieve physical verification signoff. Each iteration between signoff verification and implementation also involves the transfer of huge data files. Furthermore, the DFM analysis and enhancements, including metal fill/CMP, litho, and critical area analysis, are now starting to affect the traditional design metrics like timing, power, and signal integrity. That means that DFM effects need to be accounted for early in the design flow with full context of the design constraints
Another growing problem is the disconnect between design and signoff models. The foundry signoff models expressed in Standard Verification Rule Format (SVRF) are intrinsically the most accurate, “golden” models. These models are constantly being updated as the process matures. The design models are typically simpler abstractions of the signoff models and designed for better runtime/accuracy tradeoffs. The design models tend to get out of sync with the signoff models during a design cycle, which could lead to late stage surprises at signoff. In addition, at 28 nm and below, there are some rules described in SVRF that simply cannot be expressed in the simpler formats used to describe the design models. As a result, the implementation tools may report the design to be DRC/DFM-clean, but the signoff physical verification tool will flag these violations.
These challenges are made worse by the fact that there is no automated way to repair the DRC/DFM violations, and the traditional flow requires the transfer of huge ASCII files between the implementation and signoff environments. The design-then-verify flow that has worked in the past is increasingly getting unmanageable and unpredictable. The result is delayed time to market and wasted engineering resources.
True Manufacturing Signoff in Place-and-Route
At 28 nm and below, the manufacturability (DRC/DFM) restrictions have become very stringent. Designers are no longer able to fix such violations late in the design cycle (post-route ECOs) without significantly impacting other metrics or iterating multiple times between design and signoff. An effective way to solve these growing manufacturing closure problems is to address them during design implementation, well before the final sign-off verification stage.
Designers need a platform that comprehensively addresses manufacturing signoff issues during the design phase. An effective manufacturing closure solution must provide the following capabilities:
- Minimize the design-to-signoff model gap by reading the actual golden signoff models during design implementation
- Be able to invoke any signoff DRC/LVS/DFM engines during design implementation to guarantee no surprises at signoff
- Automatically fix any signoff violations that are identified concurrently with the traditional design metrics like multi-mode multi-corner timing, signal integrity (SI), and power
- Provide tight integration between the design implementation and verification tools at the database level and eliminate ASCII data transfer between them
The solution should enable the designer to ensure that the implementation is signoff-clean without leaving the place and route environment. The manufacturing issues can then be identified and automatically fixed during design phase. The solution should automatically address the manufacturing issues without degrading the traditional design metrics such as timing, SI, and power in order to output a design that is truly optimized and meets all performance and manufacturing requirements. The solution should compensate for any potential mismatches between signoff and design models.
An example of this type of solution is the recently announced Mentor Graphics Calibre InRoute platform, built on Mentor’s Calibre and Olympus-SoC place and route systems. Calibre InRoute provides an API- level integration of the Olympus-SoC and Calibre architectures allowing users to invoke any Calibre DRC/LVS/DFM facility inside the design environment—at the block or full-chip level—to detect and fix DRC, LVS or DFM violations at any point during design implementation.
Any signoff violation identified by any Calibre engine is automatically repaired by the router and incrementally verified to ensure that no new violations have been created. C-level APIs and a hosted data model eliminate the traditional ASCII-based data transfer between implementation and verification engines.
In Practice: DRC/DFM Signoff in Place-and-Route
The traditional manufacturing closure process that typically take weeks or months can be reduced to days by eliminating the iterations required for DRC/DFM signoff. Consider a 2-million gate, 40-nm design example to demonstrate the value of signoff verification within place and route.
In the traditional flow for this design, illustrated in Figure 3, it went through place and route and was deemed DRC/DFM clean by the physical design team. The GDSII was streamed out and transferred to the signoff team for verification signoff, while the design team continued with their timing ECOs. The signoff team ran the physical verification checks and provided manual feedback to the implementation team on the violations that needed to be fixed. The design team then implemented the recommended fixes without knowing if they created any new violations. The two teams went back and forth until most of the violations were fixed, although the market deadlines forced them to sacrifice performance. This particular design required 10 iterations over a period of three weeks to tape-out. The ECO iterations were primarily due to:
- High metal density – DRC violations caused by metal density on higher layers, specifically on the power nets. These violations had to be fixed without compromising the integrity of the power structure.
- Discrepancy between SVRF and LEF technology file – One of the complex DRC rules could not be effectively defined in the technology LEF file used during implementation. When the signoff DRC check was run using the SVRF deck, about 1500 new violations were detected.
- Discrepancy between LEF abstract and GDS views for macros – For one of the macros in the design, the abstracted LEF view was outdated and out of synch with the GDS view. When signoff DRC was run with the full GDS view, 600 additional DRC violations were detected.
Figure 3. Traditional flow in which design implementation and signoff are decoupled requires multiple file transfers and iterations between tools.
The design team then repeated the tapeout using a new flow that calls signoff DRC/DFM functions in the design environment. The implementation team detected all the signoff DRC/DFM violations and automatically fixed them from within the place-and-route tool. Model discrepancies were eliminated by the use of the golden signoff SVRF rule deck during design, and there were no file transfers between tools.
Figure 4. A new design and verification platform for advanced node designs uses true signoff rules to detect and automatically fix violations within the implementation environment.
The three types of violations were detected and fixed automatically in an efficient manner without leaving the implementation environment.
1. High metal density – The high metal density DRC violations were analyzed and fixed in context of the timing and power metrics of the design. This ensured that the power network integrity was maintained and the fixes were also guaranteed signoff clean in Calibre.
2. Discrepancy between SVRF and LEF technology file – Because implementation and signoff use the same SVRF rule decks, the complex DRC rule that was missed earlier was analyzed and fixed during implementation. No new violations were found during the final signoff.
3. Discrepancy between LEF abstract and GDS views for macros – The designer was able to load in the GDS views of all the macros in place and route tool, check for DRC violations with signoff rules, and then automatically fix them with the layout router. This ensured that the discrepancies between GDS and abstract views were eliminated and no new violations were found during the final signoff run.
The new flow reduced the signoff closure time from three weeks to three days. The ability to invoke true manufacturing signoff analysis and then automatically fix violations in the place and route environment drastically reduced the number of iterations and eliminates data transfer between implementation and signoff environments.
The escalating challenges of DRC/DFM closure pose a threat to the performance, yield, and time to market of advanced node designs. For 28 nm and below, the industry needs to adopt new design and manufacturing closure platforms that can perform true signoff from within the place and route environment. These must support advanced DRC/DFM analysis and automated repair to produce designs that are optimized for all the design metrics, boost productivity, and speed time to closure. In this way, the industry can ensure competitive, manufacturable, high-yield nanometer IC products.
Ivailo Nedelchev is a principal technologist in the Place and Route division at Mentor Graphics. Ivailo is an EDA veteran with over of 15 years of experience. Prior to Mentor, he held R&D positions at Synopsys. Ivailo’s primary interests are power analysis and optimization, multi-voltage design flow and database managements. Ivailo holds a Doctorate degree in Computer Science from Surrey University, England.
Alexander Volkov is a principal technologist in the Place and Route division at Mentor Graphics. Alex has over 15 years of industry experience acquired in various capacities at Gambit DA, Synopsys, and Sun Microsystems. Alex is the main architect of the routing engine and leads the routing R&D team at Mentor. Alex holds a Masters degree in Computer Design from the Moscow Institute of Physics and Technology.