San Jose, California – August 16, 2010 – InPA Systems, Inc. has been formed to develop and market FPGA-based rapid prototyping technology that allows users to employ the company’s patent pending Active Debug including full visibility technology to better detect hardware faults and reduce the FPGA P&R iterations associated with the debug cycle for next-generation complex SoCs.

InPA’s Active Debug technology allows users unprecedented visibility and control of the verification and validation process when integrating software and hardware onto SoC designs, a major technological leap in reducing today’s highly iterative process of “blind” or passive probing required when using current prototyping debug methods.

“We use FPGA prototypes extensively for our SoC design projects as it has become an essential hardware verification and software application validation tool,” said Dr. Gene Chuang, SoC Technical Director, Wireless Broadband Technology Division of ITRI in Taiwan.

Chuang continued, “While FPGA prototypes are popular, they are also difficult to use. We are excited to see that the InPA Systems Active Debug including full visibility technology will make our FPGA prototype verification environment even more powerful and easy to use and look forward to using their product when it’s released.”

InPA Systems was founded in October 2007 by two longtime EDA entrepreneurs: noted logic emulation authority Thomas Huang, who is chairman and CTO; and verification expert Michael Chang, who is president and CEO. Both Huang and Chang have founded a number of startups and bring a wealth of expertise in logic emulation, rapid prototyping and verification to InPA.

They hold ten patents in the areas of logic emulation and equivalence checking. InPA Systems is privately funded and has recruited a board of key advisors with vast and noteworthy academic, EDA and IC design industry credentials and expertise. Along with Huang and Chang, outside advisors are: http://www.inpasystems.com/about/advisors.php, former CEO or president of companies such as Kilopass, Synplicity and Epic; and Michel Courtoy, former CEO at Certess, Sean Torsney, former VP of marketing and sales at Verplex and currently VP marketing and sales at VisualOn, and Kazuyuki Kawauchi, held senior management positions at Fujitsu Semiconductor Limited in Japan and at Fujitsu Microelectronics America and is currently president of D2S KK.

InPA Systems is entering into one of the fastest growing EDA segments–rapid prototyping. According to InPA estimates, the rapid prototype sub-segment of the EDA market has had a CAGR of better than 20% over the last 5 years and is poised to grow even faster over the next couple of years. InPA believes that more new technology and attention will be focused on this sub-segment in the near future, making FPGA prototypes even more popular.

Technology differentiation

The key to InPA Systems’ next generation rapid prototyping debug product is its Active Debug including full visibility technology. For the first time, users gain control when running the design, at speed, in the validation process, allowing them to capture complex scenarios in the FPGAs and analyze system faults with full signal visibility. Current passive debug technology requires a highly iterative and mostly, blind process that requires the user to continually guess where system faults might be located on the SoC. The primary benefit of Active Debug including full visibility technology is that it compresses the time it takes to integrate hardware and software and to debug SoC designs.

“It’s become obvious to most all SoC design teams that FPGA-based prototype boards are invaluable when verifying the hardware and validating software applications in system,” said Mike Dini, CEO of The Dini Group. “What’s been missing is the ability to efficiently debug a multi-FPGA system. We champion InPA Systems’ efforts to bring their Active Debug including full visibility technology to market to vastly improve the way our multi-FPGA systems are debugged.”

Executive team

Huang is probably best known as a co-founder and the CTO of PiE Design Systems, a pioneering logic emulation company. He joined Quickturn when that company acquired PiE. Huang was also EVP and CTO of Aptix, a rapid prototyping company and founded several other companies in the emulation and ATE areas. He holds nine patents covering various aspects of logic emulation.

Chang is the highly-regarded co-founder, CEO and president of Verplex, a formal verification company that was acquired by Cadence. He spent a number of years at Cadence as VP and GM of the formal verification group there. Chang also founded DFT vendor Checklogic that was acquired by Mentor Graphics and holds a patent in equivalence checking.

Joe Gianelli is vice president of marketing and business development. Gianelli joined InPA after a successful launch and acquisition of Taray Inc. Before that he spent a decade-long stint at Synplicity, Inc., where he joined its executive staff as VP business development. Gianelli is a veteran of the EDA industry, having held technical and business positions at Synopsys, Epic Design Technology, Meta Software, and Cadence Design Systems.

Ecosystem and product

InPA is in the process of building its partnership ecosystem with EDA and FPGA prototype providers and key distribution companies who are focused on the rapid prototype market segment, so that the company can offer customers a completely integrated product. These partnerships will be announced over the next few months. The company expects its first product to be available in 4Q 2010.

About InPA Systems

InPA is an innovator in the debug of FPGA-based rapid prototyping. The company integrates RTL simulation, hardware and software debug environments, provides an Active Debug methodology and enables full visibility into the multi-FPGA prototype to compress the time it takes to debug SoC designs. Privately held and funded, InPA was founded in 2007 in San Jose.

Its corporate headquarters is at 22 Great Oaks Blvd. Suite 280, San Jose, CA 95119-1457, phone: (408) 362-1541, fax: (408) 362-9087. On the Web at: http://inpasystems.com/

SANTA CLARA, CA and AUSTIN, TX–(Marketwire – August 17, 2010) –  FLASH MEMORY SUMMIT and THE INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN —Lyric Semiconductor, Inc. a DARPA- and venture-funded MIT spin-out, today emerged from stealth mode to launch a new technology called probability processing, which is poised to deliver a fundamental change in processing performance and power consumption. With over a decade of development at MIT and at Lyric Semiconductor, Lyric’s probability processing technologycalculates in a completely new way, enabling orders-of-magnitude improvement in processor efficiency. Lyric Error Correction (LEC™) for flash memory, the first commercial application of probability processing, offers a 30X reduction in die size and a 12X improvement in power consumption all at higher throughput compared to today’s digital solutions.

Lyric Semiconductor has developed an alternative to digital computing. The company is redesigning processing circuits from the ground up to natively process probabilities — from the gate circuits to the processor architecture to the programming language. As a result, many applications that today require a thousand conventional processors will soon run in just one Lyric processor, providing 1,000X efficiencies in cost, power, and size.

For over 60 years, computers have been based on digital computing principles. Data is represented as bits (1s and 0s). Boolean logic gates perform operations on these bits. Lyric has invented a new kind of logic gate circuit that uses transistors as dimmer switches instead of as on/off switches. These circuits can accept inputs and calculate outputs that are between 0 and 1, directly representing probabilities — levels of certainty.

A digital processor steps through these operations serially in order to perform a function. In order to improve efficiency even further, Lyric’s processors are designed to perform many probability computations in parallel.

Lyric’s approach can accelerate search, fraud detection, spam filtering, financial modeling, genome sequence analysis, and many other important present and future applications that involve simultaneously considering many possible alternatives and deciding on the best fit — the best guess for the answer. In theory, digital processors can perform these calculations, but in practice, they do so very inefficiently. As a result, a huge amount of processing overhead is required, costing an enormous amount of space, power and money.

“After a decade of development, we have no shortage of opportunities for our probability processing technology, but we are currently focused on a modest list of both short and long-term applications that will see enormous gains in performance,” says Lyric Semiconductor CEO and co-founder Ben Vigoda. “We are starting with Lyric Error Correction but ultimately plan to develop a more general purpose probability processor that will truly change the landscape for many applications.”

Lyric Error Correction (LEC™) for Flash Memory

Flash error rates have become increasingly problematic with each new generation of the technology. Today, one in every thousand bits stored in a flash memory comes out wrong when the memory is read. In the next generation, the number of errors will approach one bit wrong in every hundred. Flash companies spend billions of dollars on new foundry processes in order to increase overall flash density, but then suffer from increasing error rates. As a result, “advanced” error correctors have had to become significantly larger, more complex and more expensive. LEC is Lyric’s first commercial probability processing offering — an advanced error corrector for flash memories that is 30X smaller and has 12X lower power consumption, all at a higher bandwidth than the digital implementations currently available.

The GP5™

Beyond today’s LEC technology, Lyric is developing the GP5™ — a general-purpose programmable probability processing platform. The GP5 will be ideally suited to calculate probabilities for all types of applications — from web searches to genome sequencing — and could enable performance gains of 1,000X over today’s digital x86-based systems such as the processors from Intel and AMD. The GP5 will run code written in Lyric’s own probability programming language called PSBL™ (Probability Synthesis to Bayesian Logic), an expressive computer programming language for working with probability based computations. Lyric will leverage its probability processor and programming technologies to deliver disruptive total systems to its customers.

Availability

Lyric’s LEC technology is currently available for license, accompanied by support services enabling product integration within 12 months. Beyond LEC, the first GP5 will begin sampling in 2013.

About Lyric Semiconductor

Lyric Semiconductor is a fabless semiconductor company founded in 2006 by MIT Ph.D. Ben Vigoda and semiconductor industry veteran David Reynolds, and is located in Cambridge, Mass. Lyric’s probability processing technology was first envisioned by Vigoda at MIT. Lyric’s lead investor and chairman of the board is Ray Stata, founder and 30-plus year CEO of Analog Devices and lead partner of Stata Venture Partners. Lyric currently employs 30 people and has received more than $20 million in government funding from DARPA and other agencies and venture investment from Stata Venture Partners. Lyric Semiconductor maintains a growing IP portfolio of 50 fundamental patent filings in the field of probability processing.

Executives from Lyric Semiconductor will be speaking at the Flash Memory Summit in the Santa Clara Convention Center, Santa Clara, Calif., and the International Symposium on Low Power Electronics and Design in Austin, Texas. CEO Ben Vigoda will be presenting at the Flash Memory Summit’s exhibit hall theatre on Wednesday, August 18 at 12:45 p.m. Pacific, and as a panelist at Session 201, Error Correcting Codes, on Thursday, August 19 at 9:50 a.m. Pacific. Also on Thursday, Théophane Weber, Lyric research scientist, will present “Low Power Logic for Statistical Signal Processing,” at Special Session One on energy-efficiency via error-resiliency at 3 p.m. Central at the Omni Hotel, Downtown Austin, Texas in Capital Ballroom A.

More information on the company and its probability processing technology can be found at its new web site, also launched today, at www.lyricsemiconductor.com.